Programmable logic controller performance enhancement by field programmable gate array based design

Programmable logic controller performance enhancement by field
programmable gate array based design
Dhruv Patel a,n
, Jignesh Bhatt b
, Sanjay Trivedi c
a
Department of Instrumentation and Control Engineering , Sardar Vallabhbhai Patel Institute of Technology (SVIT), Vasad 388306, Gujarat, India
b
Department of Instrumentation and Control Engineering, Faculty of Technology, Dharmsinh Desai University, Nadiad 387001, Gujarat, India
c
Space Application Center (SAC), Indian Space Research Organization (ISRO), Ahmedabad 380015, Gujarat, India
a r t i c l e i n f o
Article history:
Received 20 August 2013
Received in revised form
27 August 2014
Accepted 30 August 2014
Available online 14 October 2014
This paper was recommended for
publication by Prof. A.B. Rad.
Keywords:
Automation
Embedded System
FPGA
GUI development
Instrumentation
PLC
a b s t r a c t
PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like
slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel
execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform
and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx’s Spartan kit for
implementation-testing and VB has been used for GUI development. Salient merits of the design include
cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption,
smaller scan time and higher speed. Various functionalities and applications like typical PLC and
industrial alarm annunciator have been developed and successfully tested. Results of simulation, design
and implementation have been reported.
& 2014 ISA. Published by Elsevier Ltd. All rights reserved.
1. Introduction
PLCs have been quite widely utilized for automatic control of
manufacturing units, especially using binary, sequential, logic,
analog as well as hybrid control algorithms [1]. PLC has been a
user-configurable, microprocessor based specialized computational
device, to handle different types of control functions and levels of
complexities [2]. PLC can monitor and control the process using its
output devices that can either go on/off (also known as discrete or
digital outputs) or vary proportionately (also known as analog
outputs). Conventional PLCs could be quite complex and are usually
built around 486 and/or Pentium based processors with plenty of
analog and digital I/Os. Early PLCs were designed to replace relay
logic systems. These PLCs were programmed using “Ladder Logic”
or “Ladder Diagram” (LD) that strongly resembles a schematic of
relay logic. Modern PLCs could be programmed in a variety of ways,
from ladder logic to more traditional programming languages such
as BASIC, C, etc. In industrial applications, LD is one of the most
popular programming method for customized PLC configuration
development. Traditionally, a typical PLC includes a microprocessor
and, LD is sequentially executed inside the microprocessor in a
cyclic scan period. Hence, PLC performance is limited by the cyclic
scan period, which depends upon program length and processing
speed of the microprocessor. PLCs are also referred to as Program-
mable Controllers or Sequential Processors as devices as they
handle step by step execution of sequence of operations for
commercial and industrial applications. Their superior reliability
and robustness along with greater flexibility have made them
particularly attractive to designers of industrial automation systems.
However, many a times, it has been observed that conventional PLC
designs are not powerful enough to cover the performance needs of
certain real-time applications. In such situations, possibility of use
of low-cost reconfigurable hardware components such as an FPGA
has been explored [3].
The main focus of the work presented has two objectives: (a) To
analyze the LD program and organize it with sequential and
parallel structure and (b) To implement the sequential and parallel
structure of the LD program with HDL inside FPGA.
Contents lists available at ScienceDirect
journal homepage: www.elsevier.com/locate/isatrans
ISA Transactions
http://dx.doi.org/10.1016/j.isatra.2014.08.019
0019-0578/& 2014 ISA. Published by Elsevier Ltd. All rights reserved.
Abbreviations: ALU, Arithmetic and Logic Unit; ASLC, Application Specific Logic
Controller; CPN, Coloured Petri Net; CPU, Central Processing Unit; FBD, Functional
Block Diagram; FPGA, Field Programmable Gate Array; FLC, Fuzzy Logic Controller;
FSM, Finite State Machine; GUI, Graphical User Interface; HDL, Hardware Descrip-
tion Language; I/O, Input/Output; IL, Instruction List; LD, Ladder Diagram; MEMS,
Micro-Electro-Mechanical Systems; PLC, Programmable Logic Controller; SFC, Seq-
uential Function Chart; RLC, Reconfigurable Logic Controller; RPS, Reactor Protec-
tion System; VB, Visual Basic; VHDL, Very High-speed integrated circuit Hardware
Description Language
n
Corresponding author.
E-mail addresses: dmpatelic@gmail.com (D. Patel),
jigneshgbhatt@gmail.com (J. Bhatt), sanjay@sac.isro.gov.in (S. Trivedi).
ISA Transactions 54 (2015) 156–168

The remaining paper has been organized as follows. Section 2
includes FPGA under Section 2.1, while the FPGA based PLC design
approach, proposed design architecture and GUI development have
been included under Section 2.2. Section 3 includes results of
literature survey to summarize and contrast the works carried out
in the same area. Under Section 4 for validation and testing of the
proposed design approach, two applications – (i) Typical PLC Ladder
Logic Functionality Application and (ii) Industrial Alarm Annuncia-
tor Application, have been presented along with brief summary and
information regarding simulation and test results. Synthesis report
for the proposed design marks the end of Section 4 with details of
device utilization. Finally, the paper ends with conclusions and list
of references utilized.
2. Materials and methods
2.1. Materials
2.1.1. FPGA
An FPGA consists of an array of uncommitted elements that
could be interconnected in a general way. Like typical ladder logic,
the interconnections between elements are user programmable.
FPGAs were introduced in 1985 by Xilinx Company. Since then,
different FPGAs have been developed by different manufacturers –
such as Actel, Altera, Plessey, Plus, Advanced Micro Devices, Quick
Logic, Algotronix, Concurrent Logic, Crosspoint Solutions, etc. [4].
FPGA being a semiconductor device, could be configured by the
customer or designer post-manufacturing as well, hence popularly
known as “re-confogurable hardware” as well as “field program-
mable devices”. FPGAs are programmed using a logic circuit
diagram or a source code in an HDL to specify how the chip would
work. FPGAs contain programmable logic components called “logic
blocks” and an hierarchy of reconfigurable interconnections that
allow the blocks to be “wired together”, somewhat like one-chip
programmable breadboard. Logic blocks could be configured to
perform complex combinational functions, or merely simple logic
gates like AND, XOR, etc. In most FPGAs, the logic blocks also
include memory elements, which may be simple flip-flops or more
complete blocks of memory. FPGAs have been quite popular today
for their parallel execution mechanism and reconfigurable hard-
ware structure [5]. Hence, we propose the approach of utilization
of FPGAs instead of conventional mp and mc for PLC design on
account of its potential for significant performance improvements
due to FPGA's parallel instruction execution capabilities.
2.2. Methods
2.2.1. FPGA based PLC design approach [7]
Our suggested approach presents design using which a general
purpose Micro-PLC could be realized using an FPGA implementa-
tion. Once FPGA is properly configured, along with suitable human
interface or GUI, the design demonstrates capability to function as
Micro-PLC with satisfactory performance and reasonable flexibil-
ity. Ladder program could be input in Micro-PLC using its pro-
gramming mode through dedicated ladder programming software.
Ladder program debugging could be carried out by the same
software itself. Thus, our suggested approach necessitates no
special training requirements for the plant engineers, as it employs
pre-configured FPGA as conventional Micro-PLC.
The pilot model of the proposed design has been developed and
presented in [6] as well as discussed at length in [7]. The design
methodology of proposed design has been shown in Fig. 1. By using
serial communication, the hex codes of 52-bit instructions data have
been transmitted using GUI to an FPGA. This 52-bit data consist coded
information regarding selection of particular rung, components and
component inputs. For a particular rung, such transmitted hex codes
have been stored in a text file first and received inside FPGA by using
UART decoding logic later. After receiving 52-bit instruction codes
separately for each rung, the corresponding logic has been dumped
into RAM block of FPGA. The depthÂ width dimensions of RAM block
are 32 bitsÂ 52 bits respectively. Out of 52 bits, 4 bits are for selection
of component operation and 48 bits are for selection of component
inputs.
2.2.2. Proposed design architecture [7]
The architecture of the proposed design has been shown in Fig. 2.
The proposed design supports 4 rungs with 4 inputs and one output
corresponding to each rung. In the design, total 12 components such
as AND, OR, Addition, Subtraction, Move, Shift Left, Shift Right, Rotate
Left, Rotate Right, Compare Equal, Compare Greater and Compare Less
functions have been used. Each rung can contain maximum
16 components, which could be selected from combination of the
12 components mentioned above along with 4 registers. Each
component input has capability of handling four external inputs
and/or outputs. AND and OR type components can handle maximum
six inputs, which can also be outputs from other rungs. For example, if
AND or OR components have used three inputs, then remaining three
input components shall have default logic (i.e. remaining three input
components have all 1's bits). ANDing and ORing components require
total 52 bits for operation. The Addition, Subtraction, Move, Compare
Equal, Compare Greater, Compare Less components require only 12
bits for operation, hence 40 bits remains unutilized. Among them, the
Most Significant Bit (MSB) from the 1st one to 4th bits have been
utilized for selection of components; 5th to 8th bits have been used as
addresses of source register and last four bits have been used for
Fig. 1. Design methodology for proposed FPGA based PLC design [7].
D. Patel et al. / ISA Transactions 54 (2015) 156–168 157

addresses of destination register. But in case of Shift Left, Shift Right,
Rotate Left, Rotate Right components, 13 bits have been used (among
them, for MSB, 1st four bits have been used for selection of
components, 5th to 8th bits have been used for register address and
next five bits shall fix up whether the source operand is immediate
data or register) and finally the remaining 39 bits have been
unutilized.
In this design, total 68 addresses are needed, out of which four
addresses are used for four inputs and 64 for all rung component
outputs. The current proposed FPGA based PLC design contains 12
components or elements in series and 6 components or elements
in parallel. We have utilized 32-bit 4-stage pipeline RISC Processor,
which has designed capacity of forming and controlling each rung
for proposed design. In this design, four processors and four RAM
blocks have been developed using VHDL coding inside FPGA. Using
serial communication, the instruction of each rung is transmitted
via GUI to FPGA RAM blocks through UART logic.
After dumping all the instructions and initial values of registers,
all the four processors shall start fetching instructions from their
respective RAM blocks. In the first stage, all processors shall fetch
52-bit instruction data from their respective RAM blocks. In the
second stage, all processors shall decode the instructions of
selected components and operands from their respective data. In
the third stage, all processors shall execute the instructions and in
final stage (data write back) all processors shall update the outputs
and registers' values respectively. In this design, each processor
has four registers with its own address. Every processor can utilize
data of all registers, but can update data only of its own register.
2.2.3. Graphical user interface development [7]
Graphical User Interface (GUI) for the proposed FPGA based PLC
design has been shown in Fig. 3, which has been developed using
Visual Basic 6.0 software for LD based application development.
UART
Decoding
Logic
Block
RAM
1
Block
RAM
2
Block
RAM
3
PLC
Rung 1
RISC
Processor
PLC
Rung 2
RISC
Processor
PLC
Rung 3
RISC
Processor
DOUTB1 [51:0]
DOUTB2 [51:0]
DOUTB3 [51:0]
DOUTB0 [51:0]
StartStartStart
INPUT[3:0]INPUT[3:0]INPUT[3:0]
Block
RAM
0
PLC
Rung 0
RISC
Processor
Start
INPUT[3:0]
FPGA
based
PLC GUI
developed
in Visual
Basic 6.0
rxd
txd
clk
reset
O0
ADDRB1 [4:0]
ADDRB0 [4:0]
ADDRB2 [4:0]
ADDRB3 [4:0]
Rung_Out0
[15:0]
Rung_Out1
[15:0]
Rung_Out2
[15:0]
Rung_Out3
[15:0]
Components
Outputs
Comp_
Input
[63:0]
Reg0_O[31:0]
Reg1_O[31:0]
Reg2_O[31:0]
Reg3_O[31:0]
O1
Reg4_O[31:0]
Reg5_O[31:0]
Reg6_O[31:0]
Reg7_O[31:0]
O2
Reg8_O[31:0]
Reg9_O[31:0]
Reg10_O[31:0]
Reg11_O[31:0]
O3
Reg12_O[31:0]
Reg13_O[31:0]
Reg14_O[31:0]
Reg15_O[31:0]
Registers
outputs
Comp_Input[63:0]
Comp_Input[63:0]
Comp_Input[63:0]
Comp_Input[63:0]
Reg(0 to 15)_O
Reg(0 to 15)_O
Reg(0 to 15)_O
Reg(0 to 15)_O
Reg(0 to 15)_O
Reg(0to15)_O
Reg(0to15)_O
FPGA
DINA0[51:0]
DINA1 [51:0]
DINA2 [51:0]
DINA3[51:0]
ADDRA0[4:0]
ADDRA1 [4:0]
ADDRA2 [4:0]
ADDRA3[4:0]
WEN0
WEN1
WEN2
WEN3
Fig. 2. Architecture of proposed FPGA based PLC design [7].
D. Patel et al. / ISA Transactions 54 (2015) 156–168158

As shown in Fig. 3, total 112 combo boxes have been used for
selection of components' operation and operand. The combo boxes
include total 16 nos. 4-bit addresses for selection of operation. The
addresses of different operations have been listed in Table 1. As
shown in Fig. 3, send data to FPGA command has been used
for sending data of particular rung to the FPGA. After completion
of all operations of each rung, start operation inside
FPGA command could be used. RS-232 serial communication is
used to interface GUI with FPGA. Browse command could be
used to browse the selected text file from path and the path
location, while execute command could be used to send
browsed file instruction data to FPGA. The design has 4 rungs
with 4 inputs and an output corresponding to each rung. Each
rung supports maximum 16 components. For selection of rung, the
option selection button could be used. Each rung includes
maximum 14 components such as ANDing, ORing, NOT, Addition,
Subtraction, Move, Shift Left, Shift Right, Rotate Left, Rotate Right,
Compare Equal, Compare Greater, Compare Less and Counter
functions. The Flow Chart of system operation for the proposed
FPGA based PLC design has been presented in Fig. 4.
3. Theory
3.1. Results of literature survey
Du et al. in [5] presented an approach to implement an existing
LD inside FPGA, while Monmassonand et al. in [8,9] presented the
state-of-the-art of FPGA technologies and design methodologies
for industrial control applications, but they have not quantified the
performance differences on diverse platforms. Soares dos Santos
et al. in [10] presented theoretical support for our proposed
Fig. 3. Development of GUI for Proposed FPGA based PLC design [7].

approach of using FPGA instead of conventional mp and mc for
industrial automation development. Although, the authors of [8]
have utilized FPGA for Fuzzy Logic Controller (FLC) development,
while our approach proposed FPGA to be utilized for PLC devel-
opment. However, [8] proved that FPGA could contribute to
relatively better performance and overall execution speed.
In order to overcome conventional PLC limitations, using the
programmable hardware solution, FPGA based PLC has been
experimented by many researchers with its reconfigurable
hardware structure and parallel execution advantage. [11–13] have
been utilized to develop understanding and application of VB,
Xilinx ISE, Spartan 3E kit and Modelsim SE.
Economakos and Economakos in [14], endorsed the proposed
approach with standard PID controller algorithm implementation,
extended the same work with floating-point design in [15] and
presented an automated framework in [16] using Bluespec synthesis
and corresponding to STL for Siemens' S7-300/400 PLCs for extension
of the work on same PID controller implementation in [14,15].
Economakos et al. in [17] present the effects of coding styles in a
translation methodology using C-based hardware design and the
corresponding high-level synthesis toolset for FPGA based PLC
development. Uzam et al. in [18] presented Petri net based approach
with implementation of asynchronous controller using circuit ele-
ments based on discrete event control system paradigm approach;
however the mapping of ladder logic onto typical FPGAs was a
lengthy process. Miyazawa et al. in [19] presented a method to
translate PLC programs from LD to VHDL, while Welch and Carletta in
[20] proposed FPGA architecture, which implements relay ladder
logic directly. Du et al. in [21] presented an optimization technique
for LD to VHDL conversion. Though the ladder diagram is almost
equivalent to PLC instruction sequence, the above-mentioned studies
of [19,21] could only examine very fundamental logic functions such
as AND, OR, NOT, and flip-flop, while providing no detailed discus-
sion about actual PLC applications. Shuichi and Masanori et al. [22]
outlined a converter to translate the PLC instruction sequence into
the logic description along with description of the design framework,
which integrated the control logic and the peripheral functions on an
FPGA chip. Nascimento et al. in [23] presented a Reconfigurable Logic
Controller (RLC) approach, based on Xilinx Virtex-II FPGA architec-
ture, operating as a virtual hardware machine. They have used formal
language, based on Petri nets or SFC for main process development.
Ichikawa et al. in [24] and Wegrzyn et al. in [25] highlighted the
flexibility and benefits of FPGA technology based on Reconfigurable
Logic Controllers (RLCs) for implementation of parallel control
strategies in natural ways similar to the earlier years. Wegrzyn and
Wegrzyn in [26] extended the previous works using colored-
interpreted Petri nets and for modeling, testing and analysis of
Industrial Application Specific Logic Controller (ASLC) using FPGA.
Silva et al. in [27] reported an implementation of real industrial
application of Garment Transport System using Petri Nets. Using the
matrix model, Quintáns et al. in [28], the Petri Nets data structure
gets created, when the design is captured, its specifications by means
of a generalized logical equations that are easily translated into the
VHDL codes by a simple algorithm. Silva et al. in [29] described
methodology to implement logic controllers with both reconfigur-
able and programmable hardware based on Petri Nets and translates
them into Instruction Lists (ILs) or into HDL codes. Ikeshita et al. in
[30] proposed an application of FPGA to high-speed programmable
controller for development of the conversion program from Sequen-
tial Function Chart (SFC) to Verilog. Chen et al. in [31] designed a
Table 1
Addresses of different components for proposed design [7]
Operation Address Operation Address
AND 0000 Compare less than 1000
OR 0001 Moving 1001
Increment countern
0010 Shift left 1010
Decrement countern
0011 Shift right 1011
Addition 0100 Rotate left 1100
Subtraction 0101 Rotate right 1101
Compare equal 0110 NOT*
Take 8th MSB bit ‘1’ for inverted
selected inputs or components outputs
Compare greater than 0111
n
Not used in FPGA design but used only in VB based GUI applications.
Fig. 4. Flow Chart of system operation for proposed FPGA based PLC design [7].

VHDL model of the whole system directly from the original system
requirements to build a controller. Abdel-Hamid et al. in [32] and
Kusilinna et al. in [33] developed an algorithm to convert Finite State
Machine (FSM) into VHDL. Adamski et al. in [34–38] contributed an
effective work for choosing Petri Net model as a substitute of ladder
diagram for manufacturing control. For dynamic setup of internal
parameters along with display of status of ongoing activities and
debugging, [39] has been presented with the input and output
monitoring system.
Dhanashri Gawali et al. in [40] presented design containing only
7 elements in series and 4 elements in parallel. Using this design, very
less scanning time could be achieved as every rung execution requires
‘2 m’ clock cycles. Thus, if ladder program comprises of ‘n’ rungs it will
require ‘2mn’clock cycles for PLC scan. ‘m’ indicates no. of components
used in rung. The design demonstrated in [40] has capability to
achieve 2.24-microsecond scan time at 100 MHz clock for largest
possible ladder logic in the design. Patil et al. in [41] presented MEMS
sensors and actuators along with increased control logic complexities
for extension of limits of conventional PLCs for high end control
system application. Shuichi Ichikawa and Ryou Ikeda in [42] presented
the framework of hardware translation tools, which translate, inte-
grate and implement the logic circuits of control system onto an FPGA.
Alonso et al. in [43] presented a prototype tool that is applicable to
relatively new model driven software development approach to
program notation.
Yoo et al. in [44] transforms Functional Block Diagram (FBD)
designs of the PLC-based software development into a
behaviorally-equivalent Verilog program for Reactor Protection
System (RPS) software development, where Ladder Diagram (LD)
designs of the PLC-based software development has been trans-
formed to a VHDL program. In [45], the conversion from IEC61131-
3 standard language to HDL and software for converting the LD
into VHDL program has been presented. The software implemen-
ted the generation of LD structure, Boolean equivalence and VHDL
program, however neither complete PLC nor PLC based applica-
tions, have been implemented. Our suggested concept of FPGA
based PLC design has been proved better compared to conven-
tional PLC in terms of scanning time and high speed. Chmiel et al.
[46,47] support similar design approach and construction of
central processing units based on bit-word architecture, for pro-
grammable logic controllers implemented in a Virtex-4 FPGA
based development platform. Gustin et al. in [48] introduce the
use of FPGA into the CPU as a part of an ALU. The paper suggests
the use of FPGA, as an extension of the ALU, with its functions, that
are implemented in the logic circuit have capabilities to enhance
the performance of the CPU. Aliane et al. in [49] presented the
methodology of utilizing Excel spreadsheets in conjunction to
Visual Basic for application programming language for data acqui-
sition and real-time control.
4. Results and discussions
4.1. Typical PLC ladder logic functionality application
4.1.1. Summary
The proposed design has been validated by implementation of
typical PLC ladder logic functionality application. The application
has been devised in which the Move function has been used to
store the data contents, transferred from source register to destina-
tion register. The Shift Left and Shift Right functions
have been used to shift the entire source register data contents for
destination data value times left and right respectively. On the other
hand, the Rotate Left function has been used to rotate the
source register data value left for the destination data value times
and the Rotate Right function for vice-versa. The Compare
Equal, Compare Less, and Compare Greater func-
tions play the role of comparing the source register value to the
destination register value and if both the values are equal, less and
greater respectively, then the register output value shall be 1 else 0.
Likewise the Subtraction and Addition functions have
been used to subtract and add the destination register value from
the source register value and the output value shall be stored in
Fig. 5. Typical PLC ladder logic functionality application diagram with components addresse [7].
Table 2
The Initial Hex value of registers for the typical PLC ladder logic [7]
Register Hex value Register Hex value
R0 00000006FFFFF R8 0000000AFFFFF
R1 0000000BFFFFF R9 00000005FFFFF
R2 0000000AFFFFF R10 00000004FFFFF
R3 00000001FFFFF R11 00000006FFFFF
R4 00000005FFFFF R12 0000000CFFFFF
R5 00000002FFFFF R13 0000000EFFFFF
R6 00000006FFFFF R14 0000000FFFFFF
R7 00000002FFFFF R15 00000007FFFFF

source register respectively. As shown in the Fig. 5, when input
switch 1 is turned ON, then the output 1 shall also be turned ON,
the register 15 value shall be stored in register 0 and the register
5 values shall be added to the updated register 0 values. The initial
values of the registers for ladder logic functionality application have
been shown in Table 2 of which each register shall have 32-bit
instruction data. When input 2 has been turned ON, then the output
2 shall also be turned ON and the register 4 values shall be
compared with register 2 values. If register 4 values have been
found less than that of register 2 values, then output of register
4 shall be 1 else 0.
4.1.2. Simulation results
The Fig.6 represents the simulation waveform for typical PLC
ladder logic functionality application by using Modelsim SE Soft-
ware. For clarity, it could be noted that in Modelsim waveform and
ADD R6, R3 ROTATE
RIGHT R8, 8
SHIFT
LEFT R5, 7
COMPARE
LESS R4, R5
ADD R0, R5MOV R0, R15
COMPARE
GREATER R13, R7
MOV R9, R8 MOV R10, R9 SUB R15, R5
Fig. 6. Simulation results for PLC ladder logic functionality application [7].

FPGA hardware design kit, the range of outputs has been from 0 to
3. The outputs 0, 1, 2 and 3 in Modelsim waveform and FPGA
hardware design kit, correspond to outputs 1, 2, 3 and 4 in ladder
logic, gate logic and GUI development respectively.
4.1.3. Test results
The laboratory implementation of typical PLC ladder logic
functionality application under test has been shown in Fig. 7. It
has been observed that, when inputs 2 and 4 have been turned
ON, outputs 2 and 4 shall also be turned ON respectively and when
inputs 1, 2 and 4 have been turned ON, outputs 1, 2 and 4 shall also
be turned ON respectively. Similarly, when inputs 1, 2, 3 and
4 have been turned ON, outputs 1, 2, 3 and 4 shall also be turned
ON respectively.
4.2. Industrial alarm annunciator application:
4.2.1. Summary
The proposed design has been validated by implementation of
industrial alarm annunciator application, presented below. Speci-
fications of inputs (e.g. switches) and outputs (e.g. red LED, buzzer,
siren alarm and fire safety alarm) for industrial alarm annunciator
application have been summarized in Table 3.
Application Logic Conditions: The alarm annunciator shall func-
tion as per under-mentioned logic conditions:
(i) When all the four inputs are turned ON, then all the four
outputs shall be turned ON.
(ii) When any three inputs are turned ON, then output 2, output
3 and output 4 shall be turned ON.
For example, if inputs 1-2-4 are turned ON then outputs 2-3-4
shall also be turned ON. Likewise, the combination of any
three inputs, i.e. 1-2-3, 1-3-4 and 2-3-4, are turned ON, then
the outputs 2-3-4 shall also be turned ON.
(iii) When any two inputs are turned ON, then output 2 and
output 4 shall also be turned ON.
For example, the combination of any two inputs, i.e. 1-2, 2-3,
3-4, 4-1, 1-3, 1-4 and 2-4, shall also turn ON the outputs 2-4.
(iv) When any one input is turned ON, then output 4 shall be
turned ON.
The ladder logic diagram and gate logic diagram for industrial
alarm annunciator application have been shown in Fig. 8. When
inputs have been connected in series and parallel, then these
arrangements shall perform like AND gate and OR gate respec-
tively. As shown in Fig. 8, 1st rung component output has been
mapped at address 00 H. However, the 2nd, 3rd and 4th rungs
input components have been mapped at addresses 10 H to 15 H,
Fig. 7. (a–c) Test results for typical PLC ladder logic functionality application [7]. (a) When input 2 and input 4 are ON, then output 2 and output 4 are ON respectively. (b)
When input 1, input 2 and input 4 are ON, then output 1, output 2 and output 4 are ON respectively. (c)When input 1, input 2, input 3 and input 4 are ON, then output 1,
output 2, output 3 and output 4 are ON respectively.
Table 3
Inputs and outputs specifications of industrial alarm annunciator application [7]
Inputs (Address) Name Outputs (Address) Name
I1 (Input 1) (40) Normally open
switch 1
O1 (Output 1) (00) Red LED
switch 2
O2 (Output 2) (01) Buzzer
switch 3
O3 (Output 3) (02) Siren alarm
switch 4
O4 (Output 4) (03) Fire safety alarm

Fig. 8. (a,b) ladder logic diagram and gate logic diagram for industrial alarm anunciator application [7]. (a) Ladder logic diagram for industrial alarm annuciator application.
(b) Gate logic diagram for industrial alarm annuciator application.

20 H to 23 H and 40 H to 43 H respectively, and their outputs have
been mapped at addresses 16 H, 24 H and 30 H respectively.
4.2.2. Simulation results
Results of simulation of “Industrial Alarm Annunciator Appli-
cation”have been presented in Fig. 9. The simulation waveforms of
inputs, outputs, clock and reset signals along with all the rungs in
execution have been displayed. Red colored arrows and suitable
nomenclatures have been suitably applied to indicate correspond-
ing pulse waveforms.
4.2.3. Test results
Laboratory implementation of industrial alarm annunciator
application has been shown in Fig. 10. Implementation of the
design has been carried out using Xilinx Spartan 3E design kit,
which inturn uses four input switches (input-1 to input-4) and
four output LEDs (output-1 to output-4). It could be observed that
the application logic conditions mentioned above have been
successfully executed. The snapshots displayed in Fig. 10(a–d)
clearly depict the test runs of the mentioned logic conditions.
4.3. Synthesis report for the proposed design
The device utilization for Spartan 3E kit, XC3S500E – Device
Family, FG320 – Package, and -4 – Speed Grade has been shown in
Table 4. The synthesis report indicates that the evaluated maximum
clock frequency, minimum input arrival time before clock, and
maximum output required time after clock of the device – have been
Reset SignalClock Signal Input Signals
Output Signals
Fig. 9. Simulation results for industrial alarm annunciator application [7].

85.653 MHz, 9.954 ns (6.392 ns logic, 3.562 ns route), and 4.28 ns
(3.863 ns logic, 0.420 ns route) respectively. In this design of max-
imum scanning operation, total 19 clock cycles have been utilized, of
which 16 clock cycles are used by all the rung 16 components,
whereas 2 clock cycles are used in input – output updation and
1 clock cycle for signal arrival before clock cycle. The maximum and
minimum processing scan time for proposed design have been
226.108 ns (19Â 11.675 nsþ4.283 ns) and 39.308 ns (3Â 11.675 nsþ
4.283 ns) respectively. As against the high and low speed processing
scan time of YASNAC J300 PLC[50], which has recorded 4 ms and
(4Â n) ms respectively, as mentioned in [50], where value “n” could be
determined from the high speed processing and total program
capacity. Eventually, it is apparent that proposed approach results
into faster scanning time compared to the conventional PLC.
5. Conclusions
In a nutshell, this approach suggests usage of FPGA in place of
typical microprocessor or microcontroller for PLC design and
presents its simplified implementation along with GUI. The
proposed design of FPGA based PLC leverages the Parallel Execu-
tion Mechanism of FPGA for parallel execution of the rungs of
ladder logic instead of the sequential execution of rungs by
traditional Microprocessor/Microcontroller based PLC. Hence, the
proposed design performs with smaller scan time, higher speed,
smaller size, lesser power consumption and higher flexibility due
to reconfigurable hardware feature of FPGA. Typical industry-
standard Xilinx Spartan 3E design kit and VHDL programming
have been used for FPGA based PLC development, while Visual
Basic is used for GUI development. The platforms used are easily
available at reasonable costs, simple and easy to modify, expand
design and user-friendly. The design has also been simulated using
Modelsim SE simulator prior to its implementation. Two applica-
tions – (i) typical PLC itself and (ii) industrial alarm annunciator
Fig. 10. (a–d) Test results for industrial alarm annunciator application [7]. (a) When any one input is ON then the output 4 is ON. (b) When any two inputs are ON, then the
output 2 and output 4 are ON respectively. (c) When any three inputs are ON, then the output 2, output 3 and output 4 are ON. (d) When all inputs are ON, then all outputs
are ON respectively.
Table 4
Device utilization for proposed design.
Device utilization summary (Estimated values)
Logic utilization Used Available Utilization
Number of slices 3298 4656 70%
Number of slice flip flops 1140 9312 12%
Number of 4 input LUTs 6315 9312 67%
Number of bonded IOBs 10 232 4%
Nuumber of BRAMs 8 20 40%
Number of GCLKs 1 24 4%

have been developed to validate and test the proposed design
approach along with prior simulations. Both the applications have
been simulated, designed, implemented and their results have
been discussed. Sometimes, FPGAs may find it little difficult to
survive in harsh industrial environments; however as main focus
of paper being application oriented, the areas such as intrinsically
safe design, enclosure protection and noise testing have been kept
outside scope of the work presented.
Acknowledgments
The authors express their grateful thanks with respectful
appreciations to the Management, Faculty Members, Researchers
and Office Bearers of Sardar Vallabhbhai Patel Institute of Tech-
nology, Vasad, 388306, Gujarat, India; Dharmsinh Desai University,
Nadiad, 387001, Gujarat, India, and Space Application Centre,
Indian Space Research Organization, Ahmedabad 380015, Gujarat,
India, for their kind co-operation, continued support and timely
help in development of the work presented.
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