SINGLE PRECISION FLOATING POINT MULTIPLIER USING SHIFT AND ADD ALGORITHM
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This paper presents the design and implementation of a single precision floating point multiplier utilizing the shift and add algorithm, adhering to the IEEE 754 binary interchange format. It highlights the importance of floating point multiplication in DSP applications and demonstrates the multiplier's performance through simulation and synthesis, achieving a 2500 ns execution time. Future work suggests exploring the booth multiplier for signed multiplication to enhance the algorithm's applicability.
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![International Journal of Innovative Research in Advanced Engineering (IJIRAE) ISSN: 2349-2163
Volume 1 Issue 5 (June 2014) http://ijirae.com
_________________________________________________________________________________________________
© 2014, IJIRAE- All Rights Reserved Page -187
Fig. 6. Floating point Multiplier Simulation
A. Observation
Time taken for execution 2500 ns
VI.CONCLUSION
This paper describes an implementation of a floating point multiplier using Shift and Add Algorithm that supports the
IEEE 754 binary interchange format; the multiplier is more precise because it doesn’t implement rounding and just
presents the significand multiplication. The multiplication time is reduced by using Shift and Add Algorithm. The design
has been simulated on Modelsim 6.3f and synthesizes on a Xilinx 9.1 and achieved better speed.
VII. FUTURE WORK
Single Precision floating point multiplier has been implemented by using Shift and Add multiplier, which consume
low power and took 2500ns to execute. With unsigned multiplication there is no need to take the sign of the number into
consideration. However in signed multiplication the same process cannot be applied because the signed number is in a
2’s compliment form which would yield an incorrect result if multiplied in a similar fashion to unsigned multiplication.
Therefore such algorithm is required which can be applicable for both numbers. Booth multiplier is such a multiplier
which is used for signed number. Booth algorithm provides a procedure for multiplying binary integers in signed-2’s
complement representation. Therefore floating point multiplier can also be implemented by using Booth Algorithm.
ACKNOWLEDGMENT
I would like to thank my guide Dr. N. N. Mhala and co-guide Prof. P. R. Lakhe for their support and guidance.
REFERENCES
[1] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008.
[2] Mohamed Al-Ashrfy, Ashraf Salem and Wagdy Anis “An Efficient implementation of Floating Point Multiplier”
IEEE Transaction on VLSI
[3] B. Fagin and C. Renard, “Field Programmable Gate Arrays and Floating Point Arithmetic,” IEEE Transactions on
VLSI, vol. 2, no. 3, pp. 365-367, 1994.
[4] L. Louca, T. A. Cook, and W. H. Johnson, “Implementation of IEEE Single Precision Floating Point Addition and
Multiplication on FPGAs,”Proceedings of 83 the IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM’96), pp. 107-116, 1996.
[5] N. Shirazi, A. Walters, and P. Athanas, “Quantitative Analysis of Floating Point Arithmetic on FPGA Based
Custom Computing Machines,” Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
(FCCM’95), pp.155-162, 1995.S. M. Metev and V. P. Veiko, Laser Assisted Microtechnology, 2nd ed., R. M.
Osgood, Jr., Ed. Berlin, Germany: Springer-Verlag, 1998.
[6] A. Jaenicke and W. Luk, "Parameterized Floating-Point Arithmetic on FPGAs", Proc. of IEEE ICASSP, 2001, vol.
2, pp.897-900.
[7] B. Lee and N. Burgess, “Parameterisable Floating-point Operations on FPGA,” Conference Record of the Thirty-
Sixth Asilomar Conference on Signals, Systems, and Computers, 2002.
[8] “DesignChecker User Guide”, HDL Designer Series 2010.2a, Mentor Graphics, 2010.
[9] “Precision® Synthesis User’s Manual”, Precision RTL plus 2010a update 2, Mentor Graphics, 2010.](https://image.slidesharecdn.com/jnec1009236-160223113435/85/SINGLE-PRECISION-FLOATING-POINT-MULTIPLIER-USING-SHIFT-AND-ADD-ALGORITHM-4-320.jpg)
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Survey On Two-Term Dot Product Of Multiplier Using Floating PointIRJET Journal This document summarizes a survey on using floating point in two-term dot product multipliers. It discusses how floating point can increase accuracy, speed, and performance while reducing delay, area, and power consumption. Floating point is commonly used in digital signal processing and graphics algorithms. The survey found that a "fused floating point" approach using both single and double precision in multiplication, addition, and subtraction can improve performance. The document then provides details on floating point number representation and the algorithms for floating point multiplication and dot product operations. It proposes that a fused floating point dot product unit using 48-bit double precision can reduce delay and silicon area compared to 32-bit single precision designs.
Implementation of an Effective Self-Timed Multiplier for Single Precision Flo...
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A High Speed Transposed Form FIR Filter Using Floating Point Dadda Multiplier
A High Speed Transposed Form FIR Filter Using Floating Point Dadda MultiplierIJRES Journal This document discusses the development of a high-speed parallel FIR filter utilizing floating-point Dadda and Booth multipliers, focusing on optimizing speed and area. The research emphasizes the performance gains achieved with the floating-point Dadda algorithm, showcasing significant power savings and improved speed over the Booth multiplier. The findings support the adoption of the Dadda-based architecture for use in digital signal processing applications, particularly adaptive filters and signal equalizers.
Jz2517611766
Jz2517611766IJERA Editor This document summarizes a research paper that simulates an IEEE 754 standard double precision floating point multiplier using VHDL. It begins by introducing floating point arithmetic and the IEEE 754 standard. It then describes the double precision floating point format which uses 64 bits total, including a 1-bit sign, 11-bit exponent, and 52-bit mantissa. The document explains that floating point multiplication involves multiplying the mantissas and adding the exponents, with an XOR of the signs. It notes that simulating a double precision multiplier requires generating 53x53 bit partial products. The objective of the research was to design an efficient double precision floating point multiplier using techniques like Booth encoding to reduce the number of partial products and speed up
Jz2517611766
Jz2517611766IJERA Editor The document presents a study on the simulation of IEEE 754 standard double precision multiplier using booth techniques, focusing on optimizing arithmetic floating-point multiplication. It discusses the design objectives, techniques for efficient multiplication, and methods to reduce power consumption while enhancing speed and accuracy. Additionally, it covers various multiplication methods like array and booth multipliers, including implementation details and simulation results using VHDL.
International Journal of Engineering Research and Development
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Bu33436438
Bu33436438IJERA Editor This paper compares shift-add and radix-4 booth multiplication methods for single precision floating point numbers, highlighting that radix-4 booth significantly reduces intermediate computations and logic elements required. Implemented in VHDL on Xilinx, the performance analysis shows that radix-4 booth algorithm uses less hardware and operates faster than shift-add. The findings emphasize the importance of minimizing logic elements in applications requiring extensive multiplication, such as robotics and digital signal processing.
Bu33436438
Bu33436438IJERA Editor The document presents a comparison between shift-add and radix-4 booth multiplication methods for single precision floating point numbers implemented in VHDL on Xilinx. It highlights that the radix-4 booth algorithm significantly reduces the number of intermediate computations and logic elements required, resulting in improved hardware efficiency and speed. Performance analysis shows radix-4 booth multiplication uses fewer resources than the shift-add method, leading to better overall performance.
An FPGA Based Floating Point Arithmetic Unit Using Verilog
An FPGA Based Floating Point Arithmetic Unit Using VerilogIJMTST Journal This document describes the design and implementation of a double precision floating point multiplier on a Virtex-6 FPGA that is compliant with the IEEE-754 standard. It breaks down the floating point multiplication algorithm into exponent addition, significand multiplication, and sign calculation blocks. The significand multiplication is further broken down into smaller 24-bit by 17-bit multiplications using DSP48E slices. It also includes blocks for rounding and exception handling. Simulation results show the design operates at 414.714 MHz with an area of 648 slices, providing higher speed and accuracy than a single precision design.
IRJET- Single Precision Floating Point Arithmetic using VHDL Coding
IRJET- Single Precision Floating Point Arithmetic using VHDL CodingIRJET Journal The document describes a VHDL implementation of single precision floating point arithmetic operations using an FPGA. It begins with an introduction to floating point arithmetic and FPGAs. It then discusses related work on floating point implementations and the IEEE 754 single precision format. The proposed algorithm and block diagram for a single precision floating point adder are presented. Simulation results demonstrating addition, subtraction, multiplication and division are also shown. The implementation of single precision floating point arithmetic using VHDL coding allows for low-cost and reprogrammable hardware. The design was synthesized using Xilinx tools and implemented on a Virtex-7 FPGA.
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTO...
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A floating-point adder (IEEE 754 floating-point.pptx
A floating-point adder (IEEE 754 floating-point.pptxNiveditaAcharyya2035 This document describes the design and implementation of a 32-bit floating point adder according to the IEEE 754 standard using VHDL. It includes block diagrams of the main components: a pre-adder block to prepare the operands, an adder block to perform the addition or subtraction, and a standardization block to normalize the result. It also provides details on the steps involved, including extracting the sign, exponent and mantissa of the operands, handling special cases like zero, infinity and NaN, aligning the exponents, performing the addition or subtraction, normalizing and rounding the result, and adjusting the exponent.
Vedic multiplier
Vedic multiplierBHUSHAN MHASKE This seminar report summarizes the design and implementation of a floating point multiplier using Vedic multiplication techniques on an FPGA. It describes the key components of a floating point multiplier, reviews existing multiplication algorithms, and introduces the ancient Vedic multiplication method. The report outlines the design of a proposed 32-bit floating point Vedic multiplier, including mantissa, exponent, and sign calculation units. Experimental results show the Vedic multiplier utilizes 9% of slices on the target FPGA and has a maximum delay of 18.872ns, demonstrating its advantages over other multipliers in terms of speed and area efficiency.
Comparison of Adders for optimized Exponent Addition circuit in IEEE754 Float...
Comparison of Adders for optimized Exponent Addition circuit in IEEE754 Float...IJERD Editor This document compares different types of adders for calculating the addition of exponent bits when multiplying single and double precision floating point numbers according to the IEEE 754 standard. It describes parallel, carry skip, and carry select adders and analyzes their maximum combinational path delays. The document proposes using carry select and carry skip adders for exponent addition in floating point multiplication circuits, as they provide improved path delays over parallel adders. It also outlines the process for calculating the sign bit and adjusting the exponent value after multiplying the significands.
Data processing and processor organisation
Data processing and processor organisationAnsariArfat The document outlines a syllabus for a data processing and processor organization course, covering topics such as fixed and floating-point arithmetic, assembly language programming, instruction types, and processor structures. It describes IEEE standards for single and double-precision formats along with examples, and details algorithms for arithmetic operations including addition, subtraction, multiplication, and division for floating-point numbers. Additionally, it introduces Booth's multiplication algorithm for efficiently multiplying signed binary integers.
Lp2520162020
Lp2520162020IJERA Editor The document presents an analysis of a single precision floating point multiplier implemented on a Virtex 2P FPGA hardware module, focusing on its three main components: the sign, exponent, and significand. It discusses the design and benefits of utilizing FPGAs for floating-point operations in high-performance applications, alongside detailing the multiplication algorithm and providing synthesis reports from simulations. The results indicate that the floating point multiplier implementation shows efficient area utilization and minimal combinational delay.
Lp2520162020
Lp2520162020IJERA Editor The document discusses the design and implementation of a single precision floating point multiplier on a Virtex 2P FPGA hardware module. It covers the architecture, algorithm for floating point multiplication, and performance analysis, emphasizing reprogrammability and parallelism in FPGA applications. The results indicate efficient implementation with small combinational delay and resource utilization on the FPGA.
IRJET - Design and Implementation of Double Precision FPU for Optimised Speed
IRJET - Design and Implementation of Double Precision FPU for Optimised SpeedIRJET Journal This document describes the design and implementation of a double precision floating point unit (FPU) for optimized speed. It discusses the need for high-speed arithmetic operations in applications such as digital signal processing. It presents the architecture of the proposed FPU, which includes blocks for floating point multiplication and addition. It also discusses the implementation of pipelined 64-bit floating point multiplication and addition units using techniques like carry lookahead addition and hybrid multiplication. Simulation results on a FPGA platform show that the proposed pipelined design achieves higher throughput than existing non-pipelined approaches.
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SINGLE PRECISION FLOATING POINT MULTIPLIER USING SHIFT AND ADD ALGORITHM
- 1. International Journal of Innovative Research in Advanced Engineering (IJIRAE) ISSN: 2349-2163 Volume 1 Issue 5 (June 2014) http://ijirae.com _________________________________________________________________________________________________ © 2014, IJIRAE- All Rights Reserved Page - 184 SINGLE PRECISION FLOATING POINT MULTIPLIER USING SHIFT AND ADD ALGORITHM Ms. Pallavi Ramteke* Dr. N. N. Mhala Prof. P. R. Lakhe Communication Engg., RTMNU Electronics Engg. RTMNU Electronics & Comm. Engg. RTMNU Abstract— Floating-point numbers are widely adopted in many applications due to their dynamic representation capabilities. Basically floating point numbers are one possible way of representing real numbers in binary format. Floating-point representation is able to retain its resolution and accuracy compared to fixed-point representations. Multiplying floating point numbers is also a critical requirement for DSP applications involving large dynamic range. The IEEE has produced a standard to define floating point representation and arithmetic which is known as IEEE 754 standards and which is the most common representation today for real numbers on computer. The IEEE 754 standard presents two different floating point formats, Binary interchange format and Decimal interchange format. This paper presents a single precision floating point multiplier based on shift and add algorithm that supports the IEEE 754 binary interchange format.. Keywords— floating point multiplier, Shift and Add Multiplier, Modelsim 6.3f simulator, Xilinx9.1 Synthesizer I. INTRODUCTION Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. Also the need of high speed multiplier is increasing as the need of high speed processors are increasing. Higher throughput arithmetic operations are important to achieve the desired performance in many real time signal and image processing applications. One of the key arithmetic operations in such applications is multiplication and the development of fast multiplier circuit has been a subject of interest over decades. Also reducing the time delay and power consumption are very essential requirements for many applications. Floating point numbers are one possible way of representing real numbers in binary format. IEEE 754 basically specifies two formats for representing floating point values. They are single precision and double precision floating point format. This paper presents a single precision floating point format. It consists of a one bit sign (S), an eight bit exponent (E), and a twenty three bit fraction (M or Mantissa). An extra bit is added to the fraction to form the significand. If the exponent is greater than 0 and smaller than 255, and there is 1 in the MSB of the significand then the number is said to be a normalized number; in this case the real number is represented by the equation (1). Significand is the mantissa with an extra MSB bit. Figure 1. IEEE single precision floating point format Z = (-1 S ) * 2 (E - Bias) * (1.M) Bias = 127 .. . Value = (-1 Sign bit ) * 2 (Exponent -127) * (1.Mantissa) II. FLOATING POINT MULTIPLICATION ALGORITHM The normalized floating point numbers have the form of Z = (-1S) * 2 (E - Bias) * (1.M). The following algorithm is used to multiply two floating point numbers. 1. Multiplying the significand; i.e. (1.M1*1.M2) (By using Shift and Add algorithm) 2. Placing the decimal point in the result. 3. Adding the exponents; i.e. (E1 + E2 – Bias) 4. Obtaining the sign; i.e. s1 xor s2 5. Normalizing the result; i.e. obtaining 1 at the MSB of the results significand. 6. Rounding the result to fit in the available bits. 7. Checking for underflow/overflow occurrence.
- 2. International Journal of Innovative Research in Advanced Engineering (IJIRAE) ISSN: 2349-2163 Volume 1 Issue 5 (June 2014) http://ijirae.com _________________________________________________________________________________________________ © 2014, IJIRAE- All Rights Reserved Page -185 Fig. 2. Floating Point Multiplier Flow Chart III. MAIN BLOCKS OF FLOATING POINT MULTIPLIER Fig. 3. Floating point multiplier block diagram A. Sign calculator The main component of Sign calculator is XOR gate. If any one of the numbers is negative then result will be negative. The result will be positive if two numbers are having same sign. B. Exponent Adder This sub-block adds the exponents of the two floating point numbers and the Bias (127) is subtracted from the result to get true result i.e. EA + EB – bias. To perform addition of two 8-bit exponents, an 8-bit ripple carry adder (RCA) is used. The Bias is subtracted using an array of ripple borrow subtractors. Fig. 4. Ripple Carry Adder C. Unsigned Multiplier (for significand multiplication) i) Shift and Add Multiplier
- 3. International Journal of Innovative Research in Advanced Engineering (IJIRAE) ISSN: 2349-2163 Volume 1 Issue 5 (June 2014) http://ijirae.com _________________________________________________________________________________________________ © 2014, IJIRAE- All Rights Reserved Page -186 This unit is used to multiply the two unsigned significand numbers and it places the decimal point in the multiplied product. The result of this significand multiplication will be called the intermediate product (IP). Multiplication is to be carried out so as not to affect the whole multiplier’s performance. In shift and add multiplier, the carry bits are passed diagonally downwards. Partial products are generated by AND the inputs of two numbers and passing them to the appropriate adder. Fig. 5. Schematic representation of Multiplier D. Normalizer The result of the significand multiplication (intermediate product) must be normalized to have a leading ‘1’ just to the left of the decimal point. The shift operation is done using combinational shift logic made by multiplexers. IV.UNDERFLOW/OVERFLOW DETECTION Underflow/Overflow means that the result’s exponent is too small/large to be represented in the exponent field. An overflow may occur while adding the two exponents or during normalization. Overflow due to exponent addition may be compensated during subtraction of the bias; resulting in a normal output value (normal operation). An underflow may occur while subtracting the bias to form the intermediate exponent. If the intermediate exponent < 0 then it’s an underflow that can never be compensated; if the intermediate exponent = 0 then it’s an underflow that may be compensated during normalization by adding 1 to it. TABLE I. NORMALIZATION EFFECT ON RESULT’S EXPONENT AND OVERFLOW/UNDERFLOW DETECTION E result Category Comments -125 ≤ E result < 0 Underflow Can’t be compensated during normalization E result = 0 Zero May turn to normalized number during normalization (by adding 1 to it) 1 < E result < 254 Normalized May result in overflow during normalization 255 ≤ E result Overflow Can’t be compensated V. SIMULATION RESULT The simulation results for corresponding inputs are shown in Fig. The simulation is done using Modelsim 6.3f and for synthesis purpose Xilinx 9.1 software is used. Considering the random floating point numbers, Inputs: a = 19.2; b = 66.6; Output: result = 1278..72;
- 4. International Journal of Innovative Research in Advanced Engineering (IJIRAE) ISSN: 2349-2163 Volume 1 Issue 5 (June 2014) http://ijirae.com _________________________________________________________________________________________________ © 2014, IJIRAE- All Rights Reserved Page -187 Fig. 6. Floating point Multiplier Simulation A. Observation Time taken for execution 2500 ns VI.CONCLUSION This paper describes an implementation of a floating point multiplier using Shift and Add Algorithm that supports the IEEE 754 binary interchange format; the multiplier is more precise because it doesn’t implement rounding and just presents the significand multiplication. The multiplication time is reduced by using Shift and Add Algorithm. The design has been simulated on Modelsim 6.3f and synthesizes on a Xilinx 9.1 and achieved better speed. VII. FUTURE WORK Single Precision floating point multiplier has been implemented by using Shift and Add multiplier, which consume low power and took 2500ns to execute. With unsigned multiplication there is no need to take the sign of the number into consideration. However in signed multiplication the same process cannot be applied because the signed number is in a 2’s compliment form which would yield an incorrect result if multiplied in a similar fashion to unsigned multiplication. Therefore such algorithm is required which can be applicable for both numbers. Booth multiplier is such a multiplier which is used for signed number. Booth algorithm provides a procedure for multiplying binary integers in signed-2’s complement representation. Therefore floating point multiplier can also be implemented by using Booth Algorithm. ACKNOWLEDGMENT I would like to thank my guide Dr. N. N. Mhala and co-guide Prof. P. R. Lakhe for their support and guidance. REFERENCES [1] IEEE 754-2008, IEEE Standard for Floating-Point Arithmetic, 2008. [2] Mohamed Al-Ashrfy, Ashraf Salem and Wagdy Anis “An Efficient implementation of Floating Point Multiplier” IEEE Transaction on VLSI [3] B. Fagin and C. Renard, “Field Programmable Gate Arrays and Floating Point Arithmetic,” IEEE Transactions on VLSI, vol. 2, no. 3, pp. 365-367, 1994. [4] L. Louca, T. A. Cook, and W. H. Johnson, “Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs,”Proceedings of 83 the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’96), pp. 107-116, 1996. [5] N. Shirazi, A. Walters, and P. Athanas, “Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines,” Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’95), pp.155-162, 1995.S. M. Metev and V. P. Veiko, Laser Assisted Microtechnology, 2nd ed., R. M. Osgood, Jr., Ed. Berlin, Germany: Springer-Verlag, 1998. [6] A. Jaenicke and W. Luk, "Parameterized Floating-Point Arithmetic on FPGAs", Proc. of IEEE ICASSP, 2001, vol. 2, pp.897-900. [7] B. Lee and N. Burgess, “Parameterisable Floating-point Operations on FPGA,” Conference Record of the Thirty- Sixth Asilomar Conference on Signals, Systems, and Computers, 2002. [8] “DesignChecker User Guide”, HDL Designer Series 2010.2a, Mentor Graphics, 2010. [9] “Precision® Synthesis User’s Manual”, Precision RTL plus 2010a update 2, Mentor Graphics, 2010.