![Jim Duckworth, WPI Verilog Module Rev A
3
Verilog types
• Constants
– parameter DIME = 10;
– parameter width = 32, nickel = 5;
– parameter quarter = 8’b0010_0101;
• Nets
– wire clock, reset_n;
– wire[7:0] a_bus;
• Registers
– reg clock, reset_n;
– reg[7:0] a_bus;
• Integer
– only for use as general purpose variables in loops
– integer n;](https://image.slidesharecdn.com/verilogforsynthesis-combinationalreva-220822115730-143bbb6f/85/Verilog-for-synthesis-combinational-rev-a-pdf-3-320.jpg)
![Jim Duckworth, WPI Verilog Module Rev A
12
Verilog wire and register data objects
• Wire – net, connects two signals together
– wire clk, en;
– wire [15:0] a_bus;
• Reg – register, holds its value from one procedural
assignment statement to the next
– Does not imply a physical register – depends on use
– reg [7:0] b_bus;](https://image.slidesharecdn.com/verilogforsynthesis-combinationalreva-220822115730-143bbb6f/85/Verilog-for-synthesis-combinational-rev-a-pdf-12-320.jpg)
![Jim Duckworth, WPI Verilog Module Rev A
13
Index and Slice
• VHDL
– Use to and downto to specify slice
– Concatenation &
• c_bus(3 downto 0) <= b_bus(7 downto 4);
• c_bus(5 downto 0) <= b_bus(7) & a_bus(6 downto 3) & ‘0’;
• Verilog
– Use colon :
– Concatenation {,}
• assign c_bus[3:0] = b_bus[7:4];
• assign c_bus[5:0] = {b_bus[7], a_bus[6:3], 1’b0};](https://image.slidesharecdn.com/verilogforsynthesis-combinationalreva-220822115730-143bbb6f/85/Verilog-for-synthesis-combinational-rev-a-pdf-13-320.jpg)
![Jim Duckworth, WPI Verilog Module Rev A
32
Top-Down Design Hierarchy
• Instantiate module (counter example with decoder)
module decoder(
input [3:0] count,
output [6:0] seven_seg
);
// instantiate decoder module in counter
// using position of ports
decoder d1 (count_val, seven_seg_val);
// or using formal and actual names
decoder d1 (.count(count_val), .seven_seg(seven_seg_val));](https://image.slidesharecdn.com/verilogforsynthesis-combinationalreva-220822115730-143bbb6f/85/Verilog-for-synthesis-combinational-rev-a-pdf-32-320.jpg)
Verilog for synthesis - combinational rev a.pdf
- 1. Jim Duckworth, WPI Verilog Module Rev A 1 Verilog – Combinational Logic Verilog for Synthesis
- 2. Jim Duckworth, WPI Verilog Module Rev A 2 Verilog – logic and numbers • Four-value logic system • 0 – logic zero, or false condition • 1 – logic 1, or true condition • x, X – unknown logic value • z, Z - high-impedance state • Number formats • b, B binary • d, D decimal (default) • h, H hexadecimal • o, O octal • 16’H789A – 16-bit number in hex format • 1’b0 – 1-bit
- 3. Jim Duckworth, WPI Verilog Module Rev A 3 Verilog types • Constants – parameter DIME = 10; – parameter width = 32, nickel = 5; – parameter quarter = 8’b0010_0101; • Nets – wire clock, reset_n; – wire[7:0] a_bus; • Registers – reg clock, reset_n; – reg[7:0] a_bus; • Integer – only for use as general purpose variables in loops – integer n;
- 4. Jim Duckworth, WPI Verilog Module Rev A 4 Operators • Bitwise – ~ negation Verilog VHDL – & and y = a & b; y = a AND b; – | inclusive or y = a | b; y = A OR b; – ^ exclusive or y = a ^ b; y = a XOR b; – y = ~(a & b); y = A NAND b; – y = ~ a; y = NOT a; • Reduction (no direct equivalent in VHDL) – Accept single bus and return single bit result • & and y = & a_bus; • ~& nand • | or y = | a_bus; • ^ exclusive or
- 5. Jim Duckworth, WPI Verilog Module Rev A 5 Operators (cont’d) • Relational (return 1 for true, 0 for false) – < less than, <= – > greater than >= • Equality – == logical equality – != logical inequality • Logical Comparison Operators – ! logical negation – && logical and – || logical or • Arithmetic Operators – + – - – *
- 6. Jim Duckworth, WPI Verilog Module Rev A 6 Operators (cont’d) • Shift – << logical shift left, (<<< arithmetic) – >> logical shift right (>>> arithmetic) • Conditional – Only in Verilog - selects one of pair expressions – ? : – Logical expression before ? is evaluated – If true, the expression before : is assigned to output – If false, expression after : is assigned to output • Y = (A > B) ? 1 : 0 • Y = (A == B) ? A + B : A – B
- 7. Jim Duckworth, WPI Verilog Module Rev A 7 Simple Combinational Example
- 8. View Technology Schematic Jim Duckworth, WPI Verilog Module Rev A 8
- 9. Jim Duckworth, WPI Module 1 9 Decoder Tutorial Demo Example sw0 sw1 led0 led1 led2 led3 led4 led5 led6 led7 sw2
- 10. Jim Duckworth, WPI Module 1 10 Verilog Source Code
- 11. Jim Duckworth, WPI Verilog Module Rev A 11 Concurrent statements • VHDL – Process – Signal assignments • Verilog – always statement – Continuous assignment - assign
- 12. Jim Duckworth, WPI Verilog Module Rev A 12 Verilog wire and register data objects • Wire – net, connects two signals together – wire clk, en; – wire [15:0] a_bus; • Reg – register, holds its value from one procedural assignment statement to the next – Does not imply a physical register – depends on use – reg [7:0] b_bus;
- 13. Jim Duckworth, WPI Verilog Module Rev A 13 Index and Slice • VHDL – Use to and downto to specify slice – Concatenation & • c_bus(3 downto 0) <= b_bus(7 downto 4); • c_bus(5 downto 0) <= b_bus(7) & a_bus(6 downto 3) & ‘0’; • Verilog – Use colon : – Concatenation {,} • assign c_bus[3:0] = b_bus[7:4]; • assign c_bus[5:0] = {b_bus[7], a_bus[6:3], 1’b0};
- 14. Jim Duckworth, WPI Verilog Module Rev A 14 Internal wires • Declare internal wires:
- 15. Jim Duckworth, WPI Verilog Module Rev A 15 Sequential Statements • VHDL – reside in process statement • Verilog – reside in an always statement – if statements (no endif) – case statements (endcase) – for, repeat while loop statements – Note: use begin and end to block sequential statements
- 16. Jim Duckworth, WPI Verilog Module Rev A 16 Decoder – always statement • 2 to 4 decoder with enable • Combinational logic using always statement with sensitivity list – similar to VHDL process – for cyclic behavior – (@) event control operator – begin .. end block statement – note reg for y
- 17. Jim Duckworth, WPI Verilog Module Rev A 17 Decoder (cont’d) • Combinational logic using always statement with sensitivity list – similar to VHDL process – for cyclic behavior – (@) event control operator – begin .. end block statement • Statements execute sequentially – if statement – case statement • Note: case expression can concatenate signals ({,}) – Sensitivity list • (a or b or c) • Verilog 2001 allows comma-separated list (a, b, c)
- 18. Decoder – CASE statement • CASE is better for this type of design - no priority – Exactly same logic produced Jim Duckworth, WPI Verilog Module Rev A 18
- 19. Decoder – 3 to 8 with CASE Jim Duckworth, WPI Verilog Module Rev A 19
- 20. Jim Duckworth, WPI Verilog Module Rev A 20 MUX example • Example multiplexer with conditional operator • Selects different values for the target signal – priority associated with series of conditions – (similar to an IF statement) i0 q i1 i2 i3 a b
- 21. Jim Duckworth, WPI Verilog Module Rev A 21 Synthesis Results – Technology Schematic O = ((I0 * I1 * I3) + (!I0 * I1 * I4) + (!I0 * !I1 * I5) + (I0 * !I1 * I2));
- 22. Mux – with CASE statement • Include all inputs on sensitivity list Elaborating module <mux_case>. WARNING:HDLCompiler:91 - "C:ece3829mux_casemux_case.v" Line 34: Signal <i> missing in the sensitivity list is added for synthesis purposes. HDL and post- synthesis simulations may differ as a result. Jim Duckworth, WPI Verilog Module Rev A 22
- 23. Mux – fixed sensitivity list • Exact same logic produced as using conditional operator Jim Duckworth, WPI Verilog Module Rev A 23
- 24. Jim Duckworth, WPI Verilog Module Rev A 24 Priority Encoder • Priority Encoder using conditional operator • Priority order determined by sequence – similar to if-else statement
- 25. Encoder – Technology Schematic ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <encoder>. Related source file is "C:ece3829encoderencoder.v". WARNING:Xst:647 - Input <i0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: inferred 2 Multiplexer(s). Unit <encoder> synthesized. =============================================================== HDL Synthesis Report Macro Statistics # Multiplexers : 2 2-bit 2-to-1 multiplexer : 2 =============================================================== Jim Duckworth, WPI Verilog Module Rev A 25
- 26. Add ‘gs’ output Jim Duckworth, WPI Verilog Module Rev A 26
- 27. Synthesize - Design Summary ========================================================================= * Design Summary * ========================================================================= Clock Information: ------------------ No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 5.456ns ========================================================================= Jim Duckworth, WPI Verilog Module Rev A 27
- 28. Implement Design Device Utilization Summary: Slice Logic Utilization: Number of Slice Registers: 0 out of 18,224 0% Number of Slice LUTs: 2 out of 9,112 1% Number used as logic: 2 out of 9,112 1% Number using O6 output only: 1 Number using O5 output only: 0 Number using O5 and O6: 1 Number used as ROM: 0 Number used as Memory: 0 out of 2,176 0% Slice Logic Distribution: Number of occupied Slices: 2 out of 2,278 1% Number of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 2 Number with an unused Flip Flop: 2 out of 2 100% Number with an unused LUT: 0 out of 2 0% Number of fully used LUT-FF pairs: 0 out of 2 0% Number of slice register sites lost to control set restrictions: 0 out of 18,224 0% Jim Duckworth, WPI Verilog Module Rev A 28
- 29. Creating adder – using LUTs Jim Duckworth, WPI Verilog Module Rev A 29
- 30. Technology Schematic Jim Duckworth, WPI Verilog Module Rev A 30
- 31. Example of simple mistake • No errors or warnings! Jim Duckworth, WPI Verilog Module Rev A 31
- 32. Jim Duckworth, WPI Verilog Module Rev A 32 Top-Down Design Hierarchy • Instantiate module (counter example with decoder) module decoder( input [3:0] count, output [6:0] seven_seg ); // instantiate decoder module in counter // using position of ports decoder d1 (count_val, seven_seg_val); // or using formal and actual names decoder d1 (.count(count_val), .seven_seg(seven_seg_val));
- 33. Jim Duckworth, WPI Verilog Module Rev A 33 Tri-state example • Using conditional operator in continuous assignment