Verilog VHDL code Decoder and Encoder

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This document summarizes an experiment that implemented 2:4, 3:8 decoders and an 8:3 encoder using Verilog. It provides the Verilog code for each implementation and includes RTL simulation output waveforms. The aim was to model the decoders and encoder using dataflow and behavioral modeling. The experiment was conducted using Xilinx ISE 9.2i software by student SHYAMVEER SINGH with roll number B-54.

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Experiment 4
Name: SHYAMVEER SINGH
Roll no. B-54
Regno. 11205816
AIM: To implement the 2:4,3:8, Decode and 8:3 encoder using
dataflow modeling and bheverioural madeling.
Apparetus: Xillinx ISE 9.2i softwere
Implementation of 2:4 Decoder:
Enable a b y0 y1 y2 y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
Verilogecode:
module dec24(a,b,en, y1,y2,y3,y4);
input a,b,en;
output y1,y2,y3,y4;
assign y1=(~a & ~b) & en;
assign y2=(~a & b) & en;
assign y3=(a & ~b) & en;
assign y4=(a & b) & en;
endmodule
RTL simulation:

Implemantation of3:8 Decoder:
Verilogcode:
module deco38(a,b,c,en,y1,y2,y3,y4,y5,y6,y7,y8);
input a,b,c,en;
output y1,y2,y3,y4,y5,y6,y7,y8;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12;
not(w1,a);
not(w2,b);
not(w3,c);
not(w4,a);
not(w5,b);
not(w6,a);

not(w7,c);
not(w8,a);
not(w9,b);
not(w10,a);
not(w11,b);
not(w12,c);
and(y1,w1,w2,w3);
and(y2,w4,w5,c);
and(y3,w6,b,w7);
and(y4,w8,b,c);
and(y5,a,w9,w10);
and(y6,a,w11,c);
and(y7,a,b,w12);
and(y8,a,b,c);
endmodule
RTL simulation:

Implementation of 3:8 Encoder:
Verilogcode:
module encode83(y0,y1,y2,i0,i1,i2,i3,i4,i5,i6,i7);
input i0,i1,i2,i3,i4,i5,i6,i7;
output y0,y1,y2;
or(y0,i4,i5,i6,i7);
or(y1,i2,i3,i6,i7);
or(y2,i1,i3,i5,i7);

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1. Experiment 4 Name: SHYAMVEER SINGH Roll no. B-54 Regno. 11205816 AIM: To implement the 2:4,3:8, Decode and 8:3 encoder using dataflow modeling and bheverioural madeling. Apparetus: Xillinx ISE 9.2i softwere Implementation of 2:4 Decoder: Enable a b y0 y1 y2 y3 1 0 0 1 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 0 0 1 Verilogecode: module dec24(a,b,en, y1,y2,y3,y4); input a,b,en; output y1,y2,y3,y4; assign y1=(~a & ~b) & en; assign y2=(~a & b) & en; assign y3=(a & ~b) & en; assign y4=(a & b) & en; endmodule RTL simulation:

2. Output waveform:

3. Implemantation of3:8 Decoder: Verilogcode: module deco38(a,b,c,en,y1,y2,y3,y4,y5,y6,y7,y8); input a,b,c,en; output y1,y2,y3,y4,y5,y6,y7,y8; wire w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12; not(w1,a); not(w2,b); not(w3,c); not(w4,a); not(w5,b); not(w6,a);

4. not(w7,c); not(w8,a); not(w9,b); not(w10,a); not(w11,b); not(w12,c); and(y1,w1,w2,w3); and(y2,w4,w5,c); and(y3,w6,b,w7); and(y4,w8,b,c); and(y5,a,w9,w10); and(y6,a,w11,c); and(y7,a,b,w12); and(y8,a,b,c); endmodule RTL simulation:

5. Output waveform:

6. Implementation of 3:8 Encoder: Verilogcode: module encode83(y0,y1,y2,i0,i1,i2,i3,i4,i5,i6,i7); input i0,i1,i2,i3,i4,i5,i6,i7; output y0,y1,y2; or(y0,i4,i5,i6,i7); or(y1,i2,i3,i6,i7); or(y2,i1,i3,i5,i7);

7. endmodule Output waveform:

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