Verilog VHDL code Parallel adder
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Experiment 5 implements a parallel adder using half adders and full adders. It uses Verilog code to design a 4-bit parallel adder with inputs a and b. The adder uses half adders for the least significant bits and full adders for the remaining bits, storing any carry bits in variables. An RTL simulation verifies the adder design works as intended by summing the parallel binary bits with carry.
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![EXPERIMENT 5
NAME: SHYAMVEER SINGH
Roll No: B-54
REG No:11205816
AIM: Implementation of parallel adder using half adder and full
adder.
APPARETUS: Xillin 9.2i
THEORY : Parallel adder use to parallel addition of the binary bits
using any addition process like half adder or full adder.
Addition will start from LSB and till MSB and if there any carry
generated than we will store it in a new variable.
TRUTH TABLE:
a 1 0 1 1
b 1 1 0 1
sum 1 0 0 0
cin 1 1 1 1
cout 1
VERILOG CODE:
module pashyam(a,b,sum,cout);
input [3:0] a,b;
output [3:0] sum;
output cout;
wire c0,c1,c2;
halfadd f1(a[0],b[0],sum[0],c0);
fa f2(a[1],b[1],c0,sum[1],c1);
fa f3(a[2],b[2],c1,sum[2],c2);
fa f4(a[3],b[3],c2,sum[3],cout);](https://image.slidesharecdn.com/1120581612780711205816-150415060721-conversion-gate01/85/Verilog-VHDL-code-Parallel-adder-1-320.jpg)
Verilog VHDL code Parallel adder
- 1. EXPERIMENT 5 NAME: SHYAMVEER SINGH Roll No: B-54 REG No:11205816 AIM: Implementation of parallel adder using half adder and full adder. APPARETUS: Xillin 9.2i THEORY : Parallel adder use to parallel addition of the binary bits using any addition process like half adder or full adder. Addition will start from LSB and till MSB and if there any carry generated than we will store it in a new variable. TRUTH TABLE: a 1 0 1 1 b 1 1 0 1 sum 1 0 0 0 cin 1 1 1 1 cout 1 VERILOG CODE: module pashyam(a,b,sum,cout); input [3:0] a,b; output [3:0] sum; output cout; wire c0,c1,c2; halfadd f1(a[0],b[0],sum[0],c0); fa f2(a[1],b[1],c0,sum[1],c1); fa f3(a[2],b[2],c1,sum[2],c2); fa f4(a[3],b[3],c2,sum[3],cout);
- 2. endmodule module fa(a,b,c,sum,carry); input a,b,c; output sum,carry; assign sum=(a^b^c); assign carry=(a&b)|(b&c)|(c&a); endmodule module halfadd(a,b,sum,carry); input a,b; output sum,carry; assign sum=((~a)&b)|(a&(~b)); assign carry=a&b; endmodule RTL Simulation: