Xilinx Cool Runner Architecture

XILINX COOL RUNNER ARCHITECTURE
Agenda for this presentation
 Overview- Xilinx CPLDs
 Xilinx CPLD Technologies
 General features
 Xilinx Cool Runner XPLA3 CPLD
 Features and Specifications
 Architecture
 Xilinx Cool Runner-II CPLD
 Features and Specifications
 Architecture
 Evaluation board
 References
Subject: Digital System Design and Testing Course : ME-Applied Electronics College: PSG College of Technology, Coimbatore-India. Date: 14/9/2015
Presented by: Saravana Kumar R Roll No: 15MR67 Faculty: Mr. Sundar Ganesh C S Page No: 1

Overview-Xilinx CPLDs
Xilinx CPLD Technologies
 Xilinx is one of the leading supplier of FPGA, SoC, MPSoC, 3D ICs, CPLDs, ect along with
the required software packages for the above programmable ASICs i.e. ‘software defined
hardware’
 Among the above products of Xilinx, Below the types of Xilinx CPLDs:
 Cool Runner CPLDs
 Cool Runner XPLA3 CPLD (Matured/Obsolete)
 Cool Runner II (Current technology)
 XA Cool Runner II (Automotive graded)
 Additional CPLDs
 XC95 series (Ex: XC9500XL)
 XA9500XL (Automotive graded)
 The scope of the presentation is to focus more on the Cool Runner CPLDs and its
architectures
 Xilinx is offering PLA based Cool Runner CPLDs with the smart interconnection
architecture
 The enhanced architecture yields high performance with low power consumption and
low cost packaging

Overview-Xilinx CPLDs
General Features
 Ultra low power, High speed
 Multi voltage I/O operation
 Wide range of macro cells and the user I/O
 In System Programing, Boundary scan test using JTAG
 Hot pluggable
 PLA architecture with 100% routability across the function blocks
 Guaranteed 1000 program/erase cycles; 20 years of data retention
 Design entry/verification using Xilinx or industry standard CAE tools (Ex: Xilinx ISE)
 Different package types (BGA, QFP, QFN)

Xilinx Cool Runner XPLA3 CPLD
Features and Specifications
 Ultra fast and very high speed
 Available in commercial grade and extended voltage (2.7V to 3.6V) industrial grade; 5V
tolerant I/O pins
 Advanced 0.35μ five layer metal EEPROM process
 3V, In-System Programmable (ISP) and Boundary Scan Test (BCS) using JTAG IEEE 1149.1
interface
 Support for complex asynchronous clocking
 Input register setup time of 2.5 ns
 Single pass logic expandable to 48 product terms
 High-speed pin-to-pin delays of 5.0 ns
 Slew rate control per output
 Security bit prevents unauthorized access
 Four output enable controls per function block
 Foldback NAND for synthesis optimization

Features and Specifications (Continued..)
 Cool Runner XPLA3 Device Family
 Cool Runner XPLA3 Packages and user I/O Pins

 Absolute Maximum Ratings
 Recommended Operating Conditions

 Programming Specifications

Architecture
 Xilinx Cool Runner XPLA3 CPLD architecture can be analyzed with the below four blocks
 High level block diagram
 Function block
 Macrocell
 IO cell
Architecture - High level block diagram
 Figure 1 shows the high level block diagram of a 128 macrocell device implementing
Cool Runner XPLA3 architecture
 It consists of function blocks that are interconnected by ZIA(Zero power Interconnect
Array). The ZIA is the virtual cross point switch.
 Each function block has 40 inputs from ZIA and contains 16 marcocells

Architecture - High level block diagram (continued…)

Architecture – Function block
 For 128 Macrocell device, there are 8 function block; each function block contains 16
marcocells. Illustrated at the below figure 2.

Architecture – Function block (Continued…)
 Each function block contains a PLA array that generates the control terms, clock terms
and logic cells.
 PLA has the fully programmable AND array followed by fully programmable OR array.
 PLA received the input directly from ZIA. There are 40 pairs of true and complementary
inputs from ZIA that feeds the 48 product terms in the array.
 Within the 48 product terms(P-terms), there are 8 local control terms (LCT[0:7])
available as a control signals to each macrocells for use as asynchronous clocks, resets,
presets and output enables. If these 8 terms are not used as control terms, then these P-
terms can join with other 40 P-terms as additional logic resources
 In each function block there are 8 foldback NAND product terms that can be used to
synthesize increased logic densities in support of wider logic equations. This feature can
be disabled by user through software. When it is unused, then foldback NAND P-terms
can be used as additional logic resources.
 16 high speed P-terms are available at each marcocell for speed critical logic.

Architecture – Function block (Continued…)
 If the macrocell requires more than one single P-term logic, then the additional 47 P-
terms can be summed up prior to the VFM (Variable function multiplexer)
 The VFM increases the logic optimization by implementing some two input logic
functions before entering the macrocell. Refer the below Figure 3.

Architecture – Macrocell
 Figure 4 shows the architecture of the macrocell used in the Cool Runner XPLA3 CPLD

Architecture – Macrocell (Continued…)
 Any marcocell can reset or preset on power up
 Each marcocell can be configured as D or T or Latch type Flip flop. Or it can be bypassed
if the marcocell is required as a combinational logic circuit.
 Each of these flip flops can be clocked from any of the eight sources or its complements.
 There are 2 global synchronous clock; 1 universal clock signal. The clock input signals
CT[4:7] can be individually configures as product/sum term equation created from the
40 signals available at function block.
 There are 2 Muxed path to ZIA. One mux selects from either the output of the VFM or the
output of the register. The other mux selects from the output of the register or from the
I/O pad of the macrocell.
 When the I/O pin is used as an output, the output buffer is enabled, and the macrocell
feedback path can be used to feed back the logic implemented in the macrocell. When an
I/O pin is used as an input, the output buffer is 3-stated and the input signal is fed into
the ZIA via the I/O feedback path.

Architecture – I/O cell
 Figure 5 shows the architecture of I/O cell used in Cool Runner XPLA3

Architecture – I/O cell (Continued…)
 The output enable(OE) Mux has 8 possible modes as shown in figure 5.
 When the I/O Cell is configured as an input (or 3-stated output), a half latch feature
exists. This half latch pulls the input High (through a weak pull-up) if the input should
float and cross the threshold. This protects the input from staying in the linear region
and causing an increased amount of power consumption. This same weak pull-up can be
enabled in software such that it is always on when the I/O Cell is configured as an input.
This weak pull up is automatically turned on when a pin is unused by the design.
 All the unused I/O pins to be left unconnected and the week pull up resistors will be
turned on. But some dedicated input pins (CLKx, INx) do not have on chip week pull up
resistors; therefore unused dedicated input pins should have the external terminations
as all the CMOS devices do not allow input to float.
 The I/O Cell is 5V tolerant when the device is powered. Each output has independent
slew rate control (fast or slow) which assists in reducing EMI emissions.

Xilinx Cool Runner-II CPLD
Features and specifications
 Industry’s fastest low power CPLD
 Multi voltage I/O operation (1.5V to 3.3V)
 Nonvolatile 0.18μ CMOS process
 1.8V, In-System Programmable (ISP) using JTAG IEEE 1532 and Boundary Scan Test
(BCS) using JTAG IEEE 1149.1 interface
 On the fly Recognition(OTF); Hot pluggable; Optional Schmitt trigger input; unsurpassed
low power management using dataGATE external signal control
 Flexible clocking modes: optional dual edged triggered registers, clock divider, cool
clock
 Global signal options with macrocell control
 Advance design security
 Open drain output option for wired OR and LED drive
 Mixed I/O compatible with 1.5V, 1.8V, 2.5V, 3.3 V logic levels
 100% product term routability across function block

Features and specifications (Continued…)
 Xilinx Cool Runner II AC parameters
 Xilinx Cool Runner II DC parameters

 Xilinx Cool Runner II Family packages and I/O count

 Xilinx Cool Runner II Family features overview

Architecture
 Xilinx Cool Runner XPLA3 CPLD architecture can be analyzed with the below four blocks
 High level block diagram
 Function block
 Macrocell
 IO cell
 DateGATE
 Clock options
Architecture - High level block diagram
 Figure 6 shows the high level block diagram whereby the Function blocks attach to pins
and interconnect to each other within the internal Advanced Interconnect Matrix(AIM)
 Each function block has 40 inputs from AIM and contains 16 marcocells
 AIM is the highly connected low power rapid switch which is directed by software. AIM
minimizes the propagation delay and power as it makes the attachment to the various
function blocks.

Architecture - High level block diagram (continued…)

Architecture – Function Block
 The CoolRunner-II CPLD FBs contain 16 macrocells, with40 entry sites for signals to
arrive for logic creation and connections. Illustration at figure 7.
 The internal logic engine is a 56 product term PLA. All FBs are identical regardless of the
number contained in the device.
 At the high level, the product terms (p-terms) reside in a programmable logic array
(PLA). This structure is extremely flexible, and very robust when compared to fixed or
cascaded product term FBs.

Architecture – Function Block (continued…)
 Classic CPLDs typically have a few product terms available for a high-speed path to a
given macrocell. They rely on capturing unused p-terms from neighboring macrocells to
expand their product term tally, when needed. The result of this architecture is a
variable timing model and the possibility of stranding unusable logic within the FB.
 But here at PLA it is different and better. First, any product term can be attached to any
OR gate inside the FB macrocell(s). Second, any logic function can have as many p-terms
as needed attached to it within the FB, to an upper limit of 56. Third, product terms can
be re-used at multiple macrocell OR functions so that within a FB, a particular logical
product need only be created once, but can be re-used up to 16 times within the FB.
Naturally, this plays well with the fitting software, which identifies product terms that
can be shared.
 Functions need not share a common clock, common set/reset, or common output enable
to take full advantage of the PLA. Also, every product term arrives with the same time
delay incurred. There are no cascade time adders for putting more product terms in the
FB. When the FB product term budget is reached, there is a small interconnect timing
penalty to route signals to another FB to continue creating logic. Xilinx design software
handles all this automatically.

Architecture – Marcocell
 Figure 8 shows the marcocell architecture used at Xilinx Cool Runner II CPLD

Architecture – Marcocell (Continued…)
 The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation.
Users can develop sum of product (SOP) logic expressions that comprise up to 40 inputs and
span 56 product terms within a single function block. The macrocell can further combine the
SOP expression into an XOR gate with another single p-term expression. The resulting logic
expression’s polarity is also selectable.
 As well, the logic function can be pure combinatorial or registered, with the storage element
operating selectably as a D or T flip-flop, or transparent latch. Available at each macrocell are
independent selections of global, function block level or local p-term derived clocks, sets,
resets, and output enables. Each macrocell flip-flop is configurable for either single edge or
DualEDGE clocking, providing either double data rate capability or the ability to distribute a
slower clock (thereby saving power). For single edge clocking or latching, either clock polarity
can be selected per macrocell.
 When configured as a D-type flip-flop, each macrocell has an optional clock enable signal
permitting state hold while a clock runs freely. Note that Control Terms (CT) are available to
be shared for key functions within the FB, and are generally used whenever the exact same
logic function would be repeatedly created at multiple macrocells. The CT product terms are
available for FB clocking (CTC), FB asynchronous set (CTS), FB asynchronous reset (CTR), and
FB output enable (CTE).
 Any macrocell flip-flop can be configured as an input register or latch, which takes in the
signal from the macrocell’s I/O pin, and directly drives the AIM. The macrocell combinational
functionality is retained for use as a buried logic node if needed. FToggle is the maximum
clock frequency to whicha T flip-flop can reliably toggle.

Architecture – I/O Cell
 Figure 9 shows the I/O cell architecture used at Xilinx Cool Runner II CPLD
 I/O blocks are primarily transceivers. However, each I/O is either automatically compliant
with standard voltage ranges or can be programmed to become so.
 In addition to voltage levels, each input can selectively arrive through Schmitt-trigger inputs.
This adds a small time delay, but substantially reduces noise on that input pin. Approximately
500 mV of hysteresis is added when Schmitt-trigger inputs are selected. All LVCMOS inputs
can have hysteresis input. Hysteresis also allows easy generation of external clock circuits.

Architecture – I/O Cell (Continued…)
 Outputs can be directly driven, 3-stated or open-drain configured. A choice of slow or
fast slew rate output signal is also available. All inputs and disabled outputs are voltage
tolerant up to 3.3V.
 The larger parts (384 and 512 macrocell) support four output banks split evenly. They
can support groupings of one, two, three, or four separate output voltage levels. This
kind of flexibility permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V in a single part.
 The Cool Runner-II family supports SSTL2-1, SSTL3-1 and HSTL-1 high-speed I/O
standards in the 128-macrocell and larger devices.
 Figure 9 details the I/O pin, where it is noted that the inputs requiring comparison to an
external reference voltage are available. These I/O standards all require VREF pins for
proper operation. The Cool Runner-II CPLD allows any I/O pin to act as a VREF pin,
granting the board layout engineer extra freedom when laying out the pins.

Architecture – DataGATE
 Figure 10 shows the DataGATE architecture of Xilinx Cool Runner II CPLD

Architecture – DataGATE (Continued…)
 Other CPLD families use a sense amplifier approach to creating product terms, which always
has a residual current component being drawn. This residual current can be several hundred
milliamps, making them unusable in portable systems. But the Cool Runner-II CPLDs use
standard CMOS methods to create the CPLD architecture and deliver the corresponding low
current consumption, by having the series switch at each I/O pin to block the arrival of free
running signals that are not interested.
 DataGATE is a logic function that drives an assertion rail threaded through the medium and
high-density CoolRunner-II CPLD parts.
 Designers can select inputs to be blocked under the control of the DataGATE function,
effectively blocking controlled switching signals so they do not drive internal chip
capacitances. Output signals that do not switch are held by the bus hold feature. Any set of
input pins can be chosen to participate in the DataGATE function
 Each pin has the ability to attach to the AIM through a DataGATE pass transistor, and thus be
blocked. A latch automatically captures the state of the pin when it becomes blocked.
 The DataGATE feature is selectable on a per pin basis. Each input pin that uses DataGATE
must be assigned a DATA_GATE attribute.
 The DataGATE enable signal is a
 dedicated DGE/I/O pin for each package in CoolRunner-II CPLDs. Upon implementation, the
software recognizes a design using DataGATE and automatically assigns this I/O pin to the
DataGATE enable control function DGE.

Architecture – Clock options – Clock Divider
 Figure 11 shows the clock divider structure
 A clock divider circuit has been included in the CoolRunner-II CPLD architecture to divide one
externally supplied global clock by standard values. The allowable values for the division are
2, 4, 6, 8, 10, 12, 14, and 16. This capability is supplied on the GCK2 pin. The resulting clock
produced has a 50% duty cycle for all possible divisions.
 The clock divider circuit has a synchronous reset (CDRST) to guarantee no spurious clocks
can carry through on to the global clock nets. When the CDRST signal is asserted, the clock
divider output is disabled after the current cycle. When the CDRST signal is deasserted the
clock divider output becomes active upon the first edge of GCK2.

Architecture – Clock options – Dual EDGE
 Figure 12 shows the shows the macrocell flip-flopwith the DualEDGE option (doubled
clock) at each macrocell.
 Each macrocell has the ability to double its input clock switching frequency.
 The source to double can be a control term clock, a product term clock or one of the
available global clocks. The ability to switch on both clock edges, also known as dual
edge triggered (DET), is vital for a number of synchronous memory interface
applications as well as certain double data rate I/O applications.

Architecture – Clock options – Cool Clock
 Figure 13 shows how CoolCLOCK is created by internal clock cascading with the divider and
DualEDGE flip-flop working together.
 In addition to the DualEDGE flip-flop, power savings can occur by combining the clock
division circuitry with the DualEDGE circuitry. This is called cool clock feature which is
available only on GCK2
 The CoolCLOCK attribute replaces the need to instantiate the clock divider and infer DET
registers.
 The CoolCLOCK feature is available on CoolRunner-II 128 macrocell devices and larger.

Evaluation Board
 Xilinx Cool Runner II CPLD evaluation board is available with the below features:

Evaluation Board (Continued…)
 Figure 14 shows the evaluation board for Xilinx Cool Runner II CPLD

Evaluation Board (Continued…)
 Figure 15 shows block of the evaluation board for Xilinx Cool Runner II CPLD

References
 http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_dev
ices/mature_and_discontinued_products/coolrunner_xpla3.html
 http://www.xilinx.com/support/index.html/content/xilinx/en/supportNav/silicon_dev
ices/cpld/coolrunner-ii.html
 Attachments
 Cool Runner XPLA
 Cool Runner II
 Cool Runner II Evaluation board

Xilinx Cool Runner Architecture

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