![Verilog coding of MUX 8X1using if else statement
module mux(d, sel, z);
input [8:0] d;
input [2:0] sel;
output z;
reg z ;
always @( d or sel)
begin
if (sel==3'b000)
z= d[0];
else if(sel==3'b001)
z= d[1];
else if(sel==3'b010)
z= d[2];
else if(sel==3'b011)
z= d[3];
else if(sel==3'b100)
z= d[4];
else if(sel==3'b101)
z= d[5];
else if(sel==3'b110)
z= d[6];
else if(sel==3'b111)
z= d[7];
end
endmodule](https://image.slidesharecdn.com/verilog-coding-of-mux-8x1-160216062741/85/Verilog-coding-of-mux-8-x1-1-320.jpg)
![verilog coding of 8x1 mux using case statement
module mux(d, sel, z);
input [8:0] d;
input [2:0] sel;
output z;
reg z ;
always @( d or sel)
begin
case(sel)
3'b000 : z=d[0];
3'b001 : z=d[1];
3'b010 : z=d[2];
3'b011 : z=d[3];
3'b100 : z=d[4];
3'b101 : z=d[5];
3'b110 : z=d[6];
3'b111 : z=d[7];
endcase
end
endmodule](https://image.slidesharecdn.com/verilog-coding-of-mux-8x1-160216062741/85/Verilog-coding-of-mux-8-x1-2-320.jpg)
Verilog coding of mux 8 x1
- 1. Verilog coding of MUX 8X1using if else statement module mux(d, sel, z); input [8:0] d; input [2:0] sel; output z; reg z ; always @( d or sel) begin if (sel==3'b000) z= d[0]; else if(sel==3'b001) z= d[1]; else if(sel==3'b010) z= d[2]; else if(sel==3'b011) z= d[3]; else if(sel==3'b100) z= d[4]; else if(sel==3'b101) z= d[5]; else if(sel==3'b110) z= d[6]; else if(sel==3'b111) z= d[7]; end endmodule
- 2. verilog coding of 8x1 mux using case statement module mux(d, sel, z); input [8:0] d; input [2:0] sel; output z; reg z ; always @( d or sel) begin case(sel) 3'b000 : z=d[0]; 3'b001 : z=d[1]; 3'b010 : z=d[2]; 3'b011 : z=d[3]; 3'b100 : z=d[4]; 3'b101 : z=d[5]; 3'b110 : z=d[6]; 3'b111 : z=d[7]; endcase end endmodule