1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
|
// Copyright 2018 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#ifndef V8_CPU_FEATURES_H_
#define V8_CPU_FEATURES_H_
#include "src/globals.h"
namespace v8 {
namespace internal {
// CPU feature flags.
enum CpuFeature {
// x86
SSE4_1,
SSSE3,
SSE3,
SAHF,
AVX,
FMA3,
BMI1,
BMI2,
LZCNT,
POPCNT,
ATOM,
// ARM
// - Standard configurations. The baseline is ARMv6+VFPv2.
ARMv7, // ARMv7-A + VFPv3-D32 + NEON
ARMv7_SUDIV, // ARMv7-A + VFPv4-D32 + NEON + SUDIV
ARMv8, // ARMv8-A (+ all of the above)
// MIPS, MIPS64
FPU,
FP64FPU,
MIPSr1,
MIPSr2,
MIPSr6,
MIPS_SIMD, // MSA instructions
// PPC
FPR_GPR_MOV,
LWSYNC,
ISELECT,
VSX,
MODULO,
// S390
DISTINCT_OPS,
GENERAL_INSTR_EXT,
FLOATING_POINT_EXT,
VECTOR_FACILITY,
MISC_INSTR_EXT2,
NUMBER_OF_CPU_FEATURES,
// ARM feature aliases (based on the standard configurations above).
VFPv3 = ARMv7,
NEON = ARMv7,
VFP32DREGS = ARMv7,
SUDIV = ARMv7_SUDIV
};
// CpuFeatures keeps track of which features are supported by the target CPU.
// Supported features must be enabled by a CpuFeatureScope before use.
// Example:
// if (assembler->IsSupported(SSE3)) {
// CpuFeatureScope fscope(assembler, SSE3);
// // Generate code containing SSE3 instructions.
// } else {
// // Generate alternative code.
// }
class V8_EXPORT_PRIVATE CpuFeatures : public AllStatic {
public:
static void Probe(bool cross_compile) {
STATIC_ASSERT(NUMBER_OF_CPU_FEATURES <= kBitsPerInt);
if (initialized_) return;
initialized_ = true;
ProbeImpl(cross_compile);
}
static unsigned SupportedFeatures() {
Probe(false);
return supported_;
}
static bool IsSupported(CpuFeature f) {
return (supported_ & (1u << f)) != 0;
}
static inline bool SupportsOptimizer();
static inline bool SupportsWasmSimd128();
static inline unsigned icache_line_size() {
DCHECK_NE(icache_line_size_, 0);
return icache_line_size_;
}
static inline unsigned dcache_line_size() {
DCHECK_NE(dcache_line_size_, 0);
return dcache_line_size_;
}
static void PrintTarget();
static void PrintFeatures();
private:
friend void V8_EXPORT_PRIVATE FlushInstructionCache(void*, size_t);
friend class ExternalReference;
// Flush instruction cache.
static void FlushICache(void* start, size_t size);
// Platform-dependent implementation.
static void ProbeImpl(bool cross_compile);
static unsigned supported_;
static unsigned icache_line_size_;
static unsigned dcache_line_size_;
static bool initialized_;
DISALLOW_COPY_AND_ASSIGN(CpuFeatures);
};
} // namespace internal
} // namespace v8
#endif // V8_CPU_FEATURES_H_
|