Changeset 109038 in webkit for trunk/Source/JavaScriptCore/assembler/ARMv7Assembler.h

Timestamp:

Feb 27, 2012, 4:31:28 PM (13 years ago)

Author:

[email protected]

Message:

Implement support for op_negate and op_bitnot in the DFG JIT
​https://bugs.webkit.org/show_bug.cgi?id=79617

Reviewed by Filip Pizlo.

Add an ArithNegate op to the DFG JIT, to implement op_negate.

This patch also adds support for op_negate to the JSVALUE64 baseline JIT
(JSVALUE32_64 already had this), so that we can profile the slowpath usage.

This is a 2.5%-3% Sunspider progression and a 1% win on Kraken.

• assembler/ARMv7Assembler.h:

(JSC::ARMv7Assembler::sub_S):

• Added sub_S from immediate.

(ARMv7Assembler):
(JSC::ARMv7Assembler::vneg):

• Added double negate.

• assembler/MacroAssemblerARMv7.h:

(JSC::MacroAssemblerARMv7::negateDouble):

• Added double negate.

(MacroAssemblerARMv7):
(JSC::MacroAssemblerARMv7::branchNeg32):

• Added.

• assembler/MacroAssemblerX86.h:

(MacroAssemblerX86):

• moved loadDouble, absDouble to common.

• assembler/MacroAssemblerX86Common.h:

(MacroAssemblerX86Common):
(JSC::MacroAssemblerX86Common::absDouble):

• implementation can be shared.

(JSC::MacroAssemblerX86Common::negateDouble):

• Added.

(JSC::MacroAssemblerX86Common::loadDouble):

• allow absDouble to have a common implementation.

• assembler/MacroAssemblerX86_64.h:

(MacroAssemblerX86_64):

• moved loadDouble, absDouble to common.

• dfg/DFGAbstractState.cpp:

(JSC::DFG::AbstractState::execute):

• support ArithNegate.

• dfg/DFGArithNodeFlagsInferencePhase.cpp:

(JSC::DFG::ArithNodeFlagsInferencePhase::propagate):

• support ArithNegate.

• dfg/DFGByteCodeParser.cpp:

(JSC::DFG::ByteCodeParser::makeSafe):

• support ArithNegate.

(JSC::DFG::ByteCodeParser::parseBlock):

• support op_negate.

• dfg/DFGCSEPhase.cpp:

(JSC::DFG::CSEPhase::performNodeCSE):

• support ArithNegate.

• dfg/DFGCapabilities.h:

(JSC::DFG::canCompileOpcode):

• support op_negate.

• dfg/DFGGraph.h:

(JSC::DFG::Graph::negateShouldSpeculateInteger):

• support ArithNegate.

• dfg/DFGNode.h:

(JSC::DFG::Node::hasArithNodeFlags):

• support ArithNegate.

• dfg/DFGPredictionPropagationPhase.cpp:

(JSC::DFG::PredictionPropagationPhase::propagate):

• support ArithNegate.

• dfg/DFGSpeculativeJIT.cpp:

(JSC::DFG::SpeculativeJIT::compileArithNegate):

• support ArithNegate.

• dfg/DFGSpeculativeJIT.h:

(SpeculativeJIT):

• support ArithNegate.

• dfg/DFGSpeculativeJIT32_64.cpp:

(JSC::DFG::SpeculativeJIT::compile):

• support ArithNegate.

• dfg/DFGSpeculativeJIT64.cpp:

(JSC::DFG::SpeculativeJIT::compile):

• support ArithNegate.

• jit/JIT.cpp:

(JSC::JIT::privateCompileMainPass):
(JSC::JIT::privateCompileSlowCases):

• Add support for op_negate in JSVALUE64.

• jit/JITArithmetic.cpp:

(JSC::JIT::emit_op_negate):
(JSC::JIT::emitSlow_op_negate):

• Add support for op_negate in JSVALUE64.

File:

• trunk/Source/JavaScriptCore/assembler/ARMv7Assembler.h (modified) (5 diffs)

trunk/Source/JavaScriptCore/assembler/ARMv7Assembler.h

@@ -585 +585 @@
         OP_VMOV_IMM_T2  = 0xEEB0,
         OP_VMRS         = 0xEEB0,
+        OP_VNEG_T2      = 0xEEB0,
         OP_VSQRT_T1     = 0xEEB0,
         OP_B_T3a        = 0xF000,
@@ -602 +603 @@
         OP_CMP_imm_T2   = 0xF1B0,
         OP_RSB_imm_T2   = 0xF1C0,
+        OP_RSB_S_imm_T2 = 0xF1D0,
         OP_ADD_imm_T4   = 0xF200,
         OP_MOV_imm_T3   = 0xF240,
@@ -650 +652 @@
         OP_VCMPb        = 0x0A40,
         OP_VCVT_FPIVFPb = 0x0A40,
+        OP_VNEG_T2b     = 0x0A40,
         OP_VSUB_T2b     = 0x0A40,
         OP_VSQRT_T1b    = 0x0A40,
@@ -1585 +1588 @@
     }
 
+    ALWAYS_INLINE void sub_S(RegisterID rd, ARMThumbImmediate imm, RegisterID rn)
+    {
+        ASSERT(rd != ARMRegisters::pc);
+        ASSERT(rn != ARMRegisters::pc);
+        ASSERT(imm.isValid());
+        ASSERT(imm.isUInt12());
+
+        m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_RSB_S_imm_T2, rn, rd, imm);
+    }
+
     // Not allowed in an IT (if then) block?
     ALWAYS_INLINE void sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
@@ -1733 +1746 @@
     {
         m_formatter.vfpOp(OP_VABS_T2, OP_VABS_T2b, true, VFPOperand(16), rd, rm);
+    }
+
+    void vneg(FPDoubleRegisterID rd, FPDoubleRegisterID rm)
+    {
+        m_formatter.vfpOp(OP_VNEG_T2, OP_VNEG_T2b, true, VFPOperand(1), rd, rm);
     }