Ignore:
Timestamp:
Aug 13, 2013, 11:59:14 AM (12 years ago)
Author:
[email protected]
Message:

[sh4] Prepare baseline JIT for DFG_JIT implementation.
​https://bugs.webkit.org/show_bug.cgi?id=119758

Patch by Julien Brianceau <​[email protected]> on 2013-08-13
Reviewed by Oliver Hunt.

  • assembler/MacroAssemblerSH4.h:
    • Introduce a loadEffectiveAddress function to avoid code duplication.
    • Add ASSERTs and clean code.
  • assembler/SH4Assembler.h:
    • Prepare DFG_JIT implementation.
    • Add ASSERTs.
  • jit/JITStubs.cpp:
    • Add SH4 specific call for assertions.
  • jit/JITStubs.h:
    • Cosmetic change.
  • jit/JITStubsSH4.h:
    • Use constants to be more flexible with sh4 JIT stack frame.
  • jit/JSInterfaceJIT.h:
    • Cosmetic change.
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/assembler/SH4Assembler.h

    r151174 r154016  
    338338
    339339    SH4Assembler()
    340     {
    341         m_claimscratchReg = 0x0;
     340        : m_claimscratchReg(0x0)
     341    {
    342342    }
    343343
    … …  
    11901190    }
    11911191
    1192     void movlImm8r(int imm8, RegisterID dst)
    1193     {
    1194         ASSERT((imm8 <= 127) && (imm8 >= -128));
    1195 
    1196         uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8);
    1197         oneShortOp(opc);
    1198     }
    1199 
    12001192    void loadConstant(uint32_t constant, RegisterID dst)
    12011193    {
    … …  
    13321324    static void changePCrelativeAddress(int offset, uint16_t* instructionPtr, uint32_t newAddress)
    13331325    {
     1326        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    13341327        uint32_t address = (offset << 2) + ((reinterpret_cast<uint32_t>(instructionPtr) + 4) &(~0x3));
    13351328        *reinterpret_cast<uint32_t*>(address) = newAddress;
    … …  
    13381331    static uint32_t readPCrelativeAddress(int offset, uint16_t* instructionPtr)
    13391332    {
     1333        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    13401334        uint32_t address = (offset << 2) + ((reinterpret_cast<uint32_t>(instructionPtr) + 4) &(~0x3));
    13411335        return *reinterpret_cast<uint32_t*>(address);
    … …  
    13751369            nop              nop
    13761370         */
    1377         ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
    1378 
    1379         offsetBits -= 4;
    1380         if (offsetBits >= -4096 && offsetBits <= 4094) {
    1381             *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1);
    1382             *(++instructionPtr) = NOP_OPCODE;
    1383             printBlockInstr(instructionPtr - 1, from.m_offset, 2);
    1384             return;
    1385         }
    1386 
    1387         changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2);
     1371        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
     1372        ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
     1373        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6);
    13881374        printInstr(*instructionPtr, from.m_offset + 2);
    13891375    }
    … …  
    13931379        uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset);
    13941380        instructionPtr -= 3;
     1381        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    13951382        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to));
    13961383    }
    … …  
    13991386    {
    14001387        uint16_t* instructionPtr = getInstructionPtr(code, where.m_offset);
     1388        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    14011389        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(value));
    14021390    }
    … …  
    14421430
    14431431        int offset = reinterpret_cast<uint32_t>(constPoolAddr) + (index * 4) - ((reinterpret_cast<uint32_t>(instructionPtr) & ~0x03) + 4);
    1444         instruction &=0xf00;
     1432        instruction &= 0x0f00;
    14451433        instruction |= 0xd000;
    14461434        offset &= 0x03ff;
    … …  
    14631451    {
    14641452        uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(where);
     1453        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    14651454        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, value);
    14661455    }
    … …  
    14781467        uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(from);
    14791468        instructionPtr -= 3;
     1469        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    14801470        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to));
    14811471    }
    … …  
    14901480            offsetBits -= 8;
    14911481            instructionPtr++;
     1482            ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    14921483            changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
    14931484            instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
    14941485            *instructionPtr = instruction;
    14951486            printBlockInstr(instructionPtr, reinterpret_cast<uint32_t>(from) + 1, 3);
    1496             return;
    1497         }
    1498 
    1499         ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
    1500         offsetBits -= 4;
    1501         if (offsetBits >= -4096 && offsetBits <= 4094) {
    1502             *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1);
    1503             *(++instructionPtr) = NOP_OPCODE;
    1504             printBlockInstr(instructionPtr - 2, reinterpret_cast<uint32_t>(from), 2);
    1505             return;
    1506         }
    1507 
    1508         changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2);
     1487            cacheFlush(instructionPtr, sizeof(SH4Word));
     1488            return;
     1489        }
     1490
     1491        ASSERT((instructionPtr[1] & 0xf0ff) == BRAF_OPCODE);
     1492        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 6);
    15091493        printInstr(*instructionPtr, reinterpret_cast<uint32_t>(from));
    15101494    }
    … …  
    15211505        SH4Word* instruction = reinterpret_cast<SH4Word*>(instructionStart);
    15221506        intptr_t difference = reinterpret_cast<intptr_t>(to) - (reinterpret_cast<intptr_t>(instruction) + 2 * sizeof(SH4Word));
    1523         int nbinst = 0;
    1524 
    1525         if ((difference >= -4096) && (difference <= 4094)) {
    1526             instruction[0] = getOpcodeGroup6(BRA_OPCODE, difference >> 1);
    1527             instruction[1] = NOP_OPCODE;
    1528             cacheFlush(instruction, sizeof(SH4Word) * 2);
    1529             return;
    1530         }
    1531 
    1532         instruction[nbinst++] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, scratchReg2, 1);
    1533         instruction[nbinst++] = getOpcodeGroup2(JMP_OPCODE, scratchReg2);
    1534         instruction[nbinst++] = NOP_OPCODE;
    1535 
    1536         if (!(reinterpret_cast<unsigned>(instruction) & 3))
    1537             instruction[nbinst++] = NOP_OPCODE;
    1538 
    1539         instruction[nbinst++] = reinterpret_cast<unsigned>(to) & 0xffff;
    1540         instruction[nbinst++] = reinterpret_cast<unsigned>(to) >> 16;
    1541         cacheFlush(instruction, sizeof(SH4Word) * nbinst);
    1542     }
    1543 
    1544     static void revertJump(void* instructionStart, void *immptr)
     1507
     1508        if ((instruction[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE) {
     1509            instruction[1] = (BRAF_OPCODE | (instruction[0] & 0x0f00));
     1510            instruction[2] = NOP_OPCODE;
     1511            cacheFlush(&instruction[1], 2 * sizeof(SH4Word));
     1512        } else {
     1513            instruction[0] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, SH4Registers::r13, 1);
     1514            instruction[1] = getOpcodeGroup2(BRAF_OPCODE, SH4Registers::r13);
     1515            instruction[2] = NOP_OPCODE;
     1516            cacheFlush(instruction, 3 * sizeof(SH4Word));
     1517        }
     1518
     1519        changePCrelativeAddress(instruction[0] & 0x00ff, instruction, difference - 2);
     1520    }
     1521
     1522    static void revertJumpToMove(void* instructionStart, RegisterID rd, int imm)
    15451523    {
    15461524        SH4Word *insn = reinterpret_cast<SH4Word*>(instructionStart);
    15471525        ASSERT((insn[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
    1548         changePCrelativeAddress(insn[0] & 0x00ff, insn, reinterpret_cast<uint32_t>(immptr));
     1526
     1527        if ((insn[1] & 0xf000) == CMPEQ_OPCODE) {
     1528            insn[0] = getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, SH4Registers::r13, insn[0] & 0x00ff);
     1529            insn[1] = (insn[1] & 0xf00f) | (rd << 8) | (SH4Registers::r13 << 4);
     1530            cacheFlush(insn, 2 * sizeof(SH4Word));
     1531            changePCrelativeAddress(insn[0] & 0x00ff, insn, imm);
     1532            return;
     1533        }
     1534
     1535        if ((insn[0] & 0x00ff) == 1)
     1536            insn[1] = getOpcodeGroup6(BRA_OPCODE, 3);
     1537        else
     1538            insn[1] = NOP_OPCODE;
     1539
     1540        insn[2] = NOP_OPCODE;
     1541        cacheFlush(&insn[1], 2 * sizeof(SH4Word));
     1542
     1543        changePCrelativeAddress(insn[0] & 0x00ff, insn, imm);
    15491544    }
    15501545
    … …  
    15591554
    15601555        if (type == JumpNear) {
    1561             ASSERT((instruction ==  BT_OPCODE) || (instruction == BF_OPCODE) || (instruction == BRA_OPCODE));
    15621556            int offset = (codeSize() - from.m_offset) - 4;
     1557            ASSERT((((instruction == BT_OPCODE) || (instruction == BF_OPCODE)) && (offset >= -256) && (offset <= 254))
     1558                || ((instruction == BRA_OPCODE) && (offset >= -4096) && (offset <= 4094)));
    15631559            *instructionPtr++ = instruction | (offset >> 1);
    15641560            printInstr(*instructionPtr, from.m_offset + 2);
    … …  
    15751571            instruction ^= 0x0202;
    15761572            *instructionPtr++ = instruction;
    1577             if ((*instructionPtr & 0xf000) == 0xe000) {
     1573            if ((*instructionPtr & 0xf000) == MOVIMM_OPCODE) {
    15781574                uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
    15791575                *addr = offsetBits;
    … …  
    15911587        */
    15921588        ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
    1593         offsetBits = (to.m_offset - from.m_offset) - 4;
    1594         if (offsetBits >= -4096 && offsetBits <= 4094) {
    1595             *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1);
    1596             *(++instructionPtr) = NOP_OPCODE;
    1597             printBlockInstr(instructionPtr - 1, from.m_offset, 2);
    1598             return;
    1599         }
     1589        offsetBits = (to.m_offset - from.m_offset) - 6;
    16001590
    16011591        instruction = *instructionPtr;
    1602         if ((instruction & 0xf000) == 0xe000) {
     1592        if ((instruction & 0xf000) == MOVIMM_OPCODE) {
    16031593            uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
    1604             *addr = offsetBits - 2;
     1594            *addr = offsetBits;
    16051595            printInstr(*instructionPtr, from.m_offset + 2);
    16061596            return;
    16071597        }
    16081598
    1609         changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2);
     1599        ASSERT((instructionPtr[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
     1600        changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
    16101601        printInstr(*instructionPtr, from.m_offset + 2);
    16111602    }
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