Changeset 189293 in webkit for trunk/Source/JavaScriptCore/offlineasm/arm.rb

Timestamp:

Sep 3, 2015, 3:16:23 PM (10 years ago)

Author:

[email protected]

Message:

Clean up register naming
​https://bugs.webkit.org/show_bug.cgi?id=148658

Reviewed by Geoffrey Garen.

This changes register naming conventions in the llint and baseline JIT
in order to use as few (native) callee-save registers as possible on
64-bits platforms. It also introduces significant changes in the way
registers names are defined in the LLint and baseline JIT in order to
enable a simpler convention about which registers can be aliased. That
convention is valid across all architecture, and described in
llint/LowLevelInterpreter.asm.

Callee save registers are now called out regCS<n> (in the JIT) or
csr<n> (in the LLInt) with a common numbering across all tiers. Some
registers are unused in some tiers.

As a part of this change, rdi was removed from the list of temporary
registers for X86-64 Windows as it is a callee saves register. This
reduced the number of temporary registers for X86-64 Windows.

This is in preparation for properly handling callee save register
preservation and restoration.

• dfg/DFGJITCompiler.cpp:

(JSC::DFG::JITCompiler::compileFunction):

• ftl/FTLLink.cpp:

(JSC::FTL::link):

• jit/FPRInfo.h:

(JSC::FPRInfo::toRegister):
(JSC::FPRInfo::toIndex):

• jit/GPRInfo.h:

(JSC::GPRInfo::toIndex):
(JSC::GPRInfo::toRegister):
(JSC::GPRInfo::debugName): Deleted.

• jit/JIT.cpp:

(JSC::JIT::privateCompile):

• jit/JITArithmetic.cpp:

(JSC::JIT::emit_op_mod):

• jit/JITOpcodes.cpp:

(JSC::JIT::emitSlow_op_loop_hint):

• jit/JITOpcodes32_64.cpp:

(JSC::JIT::emit_op_end):
(JSC::JIT::emit_op_new_object):

• jit/RegisterPreservationWrapperGenerator.cpp:

(JSC::generateRegisterPreservationWrapper):
(JSC::generateRegisterRestoration):

• jit/ThunkGenerators.cpp:

(JSC::arityFixupGenerator):
(JSC::nativeForGenerator): Deleted.

• llint/LowLevelInterpreter.asm:
• llint/LowLevelInterpreter32_64.asm:
• llint/LowLevelInterpreter64.asm:
• offlineasm/arm.rb:
• offlineasm/arm64.rb:
• offlineasm/cloop.rb:
• offlineasm/mips.rb:
• offlineasm/registers.rb:
• offlineasm/sh4.rb:
• offlineasm/x86.rb:

File:

• trunk/Source/JavaScriptCore/offlineasm/arm.rb (modified) (2 diffs)

trunk/Source/JavaScriptCore/offlineasm/arm.rb

@@ -27 +27 @@
 require "opt"
 require "risc"
+
+# GPR conventions, to match the baseline JIT
+#
+#  x0 => t0, a0, r0
+#  x1 => t1, a1, r1
+#  x2 => t2, a2, r2
+#  x3 => t3, a3, r3
+#  x6 =>            (callee-save scratch)
+#  x7 => cfr        (ARMv7 only)
+#  x8 => t4         (callee-save)
+#  x9 => t5         (callee-save)
+# x10 =>            (callee-save scratch)
+# x11 => cfr        (ARM and ARMv7 traditional)
+# x12 =>            (callee-save scratch)
+#  lr => lr
+#  sp => sp
+#  pc => pc
+#
+# FPR conventions, to match the baseline JIT
+#
+# d0 => ft0, fa0, fr
+# d1 => ft1, fa1
+# d2 => ft2
+# d3 => ft3
+# d4 => ft4
+# d5 => ft5
+# d6 =>              (scratch)
+# d7 =>              (scratch)
 
 def isARMv7
@@ -120 +148 @@
     def armOperand
         case name
-        when "ft0", "fr"
+        when "ft0", "fr", "fa0"
             "d0"
-        when "ft1"
+        when "ft1", "fa1"
             "d1"
         when "ft2"