Changeset 189293 in webkit for trunk/Source/JavaScriptCore/offlineasm/arm64.rb

Timestamp:

Sep 3, 2015, 3:16:23 PM (10 years ago)

Author:

[email protected]

Message:

Clean up register naming
​https://bugs.webkit.org/show_bug.cgi?id=148658

Reviewed by Geoffrey Garen.

This changes register naming conventions in the llint and baseline JIT
in order to use as few (native) callee-save registers as possible on
64-bits platforms. It also introduces significant changes in the way
registers names are defined in the LLint and baseline JIT in order to
enable a simpler convention about which registers can be aliased. That
convention is valid across all architecture, and described in
llint/LowLevelInterpreter.asm.

Callee save registers are now called out regCS<n> (in the JIT) or
csr<n> (in the LLInt) with a common numbering across all tiers. Some
registers are unused in some tiers.

As a part of this change, rdi was removed from the list of temporary
registers for X86-64 Windows as it is a callee saves register. This
reduced the number of temporary registers for X86-64 Windows.

This is in preparation for properly handling callee save register
preservation and restoration.

• dfg/DFGJITCompiler.cpp:

(JSC::DFG::JITCompiler::compileFunction):

• ftl/FTLLink.cpp:

(JSC::FTL::link):

• jit/FPRInfo.h:

(JSC::FPRInfo::toRegister):
(JSC::FPRInfo::toIndex):

• jit/GPRInfo.h:

(JSC::GPRInfo::toIndex):
(JSC::GPRInfo::toRegister):
(JSC::GPRInfo::debugName): Deleted.

• jit/JIT.cpp:

(JSC::JIT::privateCompile):

• jit/JITArithmetic.cpp:

(JSC::JIT::emit_op_mod):

• jit/JITOpcodes.cpp:

(JSC::JIT::emitSlow_op_loop_hint):

• jit/JITOpcodes32_64.cpp:

(JSC::JIT::emit_op_end):
(JSC::JIT::emit_op_new_object):

• jit/RegisterPreservationWrapperGenerator.cpp:

(JSC::generateRegisterPreservationWrapper):
(JSC::generateRegisterRestoration):

• jit/ThunkGenerators.cpp:

(JSC::arityFixupGenerator):
(JSC::nativeForGenerator): Deleted.

• llint/LowLevelInterpreter.asm:
• llint/LowLevelInterpreter32_64.asm:
• llint/LowLevelInterpreter64.asm:
• offlineasm/arm.rb:
• offlineasm/arm64.rb:
• offlineasm/cloop.rb:
• offlineasm/mips.rb:
• offlineasm/registers.rb:
• offlineasm/sh4.rb:
• offlineasm/x86.rb:

File:

• trunk/Source/JavaScriptCore/offlineasm/arm64.rb (modified) (3 diffs)

trunk/Source/JavaScriptCore/offlineasm/arm64.rb

@@ -38 +38 @@
 # GPR conventions, to match the baseline JIT:
 #
-#  x0  => return value, cached result, first argument, t0, a0, r0
+#  x0  => t0, a0, r0
 #  x1  => t1, a1, r1
 #  x2  => t2, a2
-#  x3  => a3
-#  x5  => t4
-#  x6  => t6
-#  x9  => (nonArgGPR1 in baseline)
-# x13  => scratch (unused in baseline)
-# x16  => scratch
-# x17  => scratch
-# x23  => t3
-# x24  => t5
-# x27  => csr1 (tagTypeNumber)
-# x28  => csr2 (tagMask)
+#  x3  => t3, a3
+#  x4  => t4
+#  x5  => t5
+# x13  =>                  (scratch)
+# x16  =>                  (scratch)
+# x17  =>                  (scratch)
+# x26  =>             csr0 (PB)
+# x27  =>             csr1 (tagTypeNumber)
+# x28  =>             csr2 (tagMask)
 # x29  => cfr
 #  sp  => sp
 #  lr  => lr
 #
-# FPR conentions, to match the baseline JIT:
+# FPR conventions, to match the baseline JIT:
 #
-#  q0  => ft0
-#  q1  => ft1
-#  q2  => ft2
-#  q3  => ft3
-#  q4  => ft4 (unused in baseline)
-#  q5  => ft5 (unused in baseline)
+#  q0  => ft0, fa0, fr
+#  q1  => ft1, fa1
+#  q2  => ft2, fa2
+#  q3  => ft3, fa3
+#  q4  => ft4          (unused in baseline)
+#  q5  => ft5          (unused in baseline)
 # q31  => scratch
 
@@ -110 +108 @@
         when 't2', 'a2'
             arm64GPRName('x2', kind)
-        when 'a3'
+        when 't3', 'a3'
             arm64GPRName('x3', kind)
-        when 't3'
-            arm64GPRName('x23', kind)
         when 't4'
+            arm64GPRName('x4', kind)
+        when 't5'
             arm64GPRName('x5', kind)
-        when 't5'
-            arm64GPRName('x24', kind)
-        when 't6'
-            arm64GPRName('x6', kind)
-        when 't7'
-            arm64GPRName('x7', kind)
         when 'cfr'
             arm64GPRName('x29', kind)
+        when 'csr0'
+            arm64GPRName('x26', kind)
         when 'csr1'
             arm64GPRName('x27', kind)
@@ -141 +135 @@
     def arm64Operand(kind)
         case @name
-        when 'ft0'
+        when 'ft0', 'fr', 'fa0'
             arm64FPRName('q0', kind)
-        when 'ft1'
+        when 'ft1', 'fa1'
             arm64FPRName('q1', kind)
-        when 'ft2'
+        when 'ft2', 'fa2'
             arm64FPRName('q2', kind)
-        when 'ft3'
+        when 'ft3', 'fa3'
             arm64FPRName('q3', kind)
         when 'ft4'