Changeset 189293 in webkit for trunk/Source/JavaScriptCore/offlineasm/sh4.rb

Timestamp:

Sep 3, 2015, 3:16:23 PM (10 years ago)

Author:

[email protected]

Message:

Clean up register naming
​https://bugs.webkit.org/show_bug.cgi?id=148658

Reviewed by Geoffrey Garen.

This changes register naming conventions in the llint and baseline JIT
in order to use as few (native) callee-save registers as possible on
64-bits platforms. It also introduces significant changes in the way
registers names are defined in the LLint and baseline JIT in order to
enable a simpler convention about which registers can be aliased. That
convention is valid across all architecture, and described in
llint/LowLevelInterpreter.asm.

Callee save registers are now called out regCS<n> (in the JIT) or
csr<n> (in the LLInt) with a common numbering across all tiers. Some
registers are unused in some tiers.

As a part of this change, rdi was removed from the list of temporary
registers for X86-64 Windows as it is a callee saves register. This
reduced the number of temporary registers for X86-64 Windows.

This is in preparation for properly handling callee save register
preservation and restoration.

• dfg/DFGJITCompiler.cpp:

(JSC::DFG::JITCompiler::compileFunction):

• ftl/FTLLink.cpp:

(JSC::FTL::link):

• jit/FPRInfo.h:

(JSC::FPRInfo::toRegister):
(JSC::FPRInfo::toIndex):

• jit/GPRInfo.h:

(JSC::GPRInfo::toIndex):
(JSC::GPRInfo::toRegister):
(JSC::GPRInfo::debugName): Deleted.

• jit/JIT.cpp:

(JSC::JIT::privateCompile):

• jit/JITArithmetic.cpp:

(JSC::JIT::emit_op_mod):

• jit/JITOpcodes.cpp:

(JSC::JIT::emitSlow_op_loop_hint):

• jit/JITOpcodes32_64.cpp:

(JSC::JIT::emit_op_end):
(JSC::JIT::emit_op_new_object):

• jit/RegisterPreservationWrapperGenerator.cpp:

(JSC::generateRegisterPreservationWrapper):
(JSC::generateRegisterRestoration):

• jit/ThunkGenerators.cpp:

(JSC::arityFixupGenerator):
(JSC::nativeForGenerator): Deleted.

• llint/LowLevelInterpreter.asm:
• llint/LowLevelInterpreter32_64.asm:
• llint/LowLevelInterpreter64.asm:
• offlineasm/arm.rb:
• offlineasm/arm64.rb:
• offlineasm/cloop.rb:
• offlineasm/mips.rb:
• offlineasm/registers.rb:
• offlineasm/sh4.rb:
• offlineasm/x86.rb:

File:

• trunk/Source/JavaScriptCore/offlineasm/sh4.rb (modified) (3 diffs)

trunk/Source/JavaScriptCore/offlineasm/sh4.rb

@@ -25 +25 @@
 require 'risc'
 
+# GPR conventions, to match the baseline JIT
+#
+#  r0 => t0, r0
+#  r1 => t1, r1
+#  r2 => t4
+#  r3 => t5
+#  r4 =>         a0
+#  r5 =>         a1
+#  r6 => t2,     a2
+#  r7 => t3,     a3
+# r10 =>            (scratch)
+# r11 =>            (scratch)
+# r13 =>            (scratch)
+# r14 => cfr
+# r15 => sp
+#  pr => lr
+
+# FPR conventions, to match the baseline JIT
+# We don't have fa2 or fa3!
+#  dr0 => ft0, fr
+#  dr2 => ft1
+#  dr4 => ft2,   fa0
+#  dr6 => ft3,   fa1
+#  dr8 => ft4
+# dr10 => ft5
+# dr12 =>             (scratch)
+
 class Node
     def sh4SingleHi
@@ -52 +79 @@
 end
 
-SH4_TMP_GPRS = [ SpecialRegister.new("r3"), SpecialRegister.new("r11"), SpecialRegister.new("r13") ]
-SH4_TMP_FPRS = [ SpecialRegister.new("dr10") ]
+SH4_TMP_GPRS = [ SpecialRegister.new("r10"), SpecialRegister.new("r11"), SpecialRegister.new("r13") ]
+SH4_TMP_FPRS = [ SpecialRegister.new("dr12") ]
 
 class RegisterID
     def sh4Operand
         case name
-        when "t0"
+        when "a0"
+            "r4"
+        when "a1"
+            "r5"
+        when "r0", "t0"
             "r0"
-        when "t1"
+        when "r1", "t1"
             "r1"
-        when "t2"
+        when "a2", "t2"
+            "r6"
+        when "a3", "t3"
+            "r7"
+        when "t4"
             "r2"
-        when "t3"
-            "r10"
-        when "t4", "a0"
-            "r4"
-        when "t5", "a1"
-            "r5"
-        when "t6", "a2"
-            "r6"
-        when "t7", "a3"
-            "r7"
-        when "t8"
-            "r8"
-        when "t9"
-            "r9"
+        when "t5"
+            "r3"
         when "cfr"
             "r14"
@@ -97 +120 @@
         when "ft1"
             "dr2"
-        when "ft2"
+        when "ft2", "fa0"
             "dr4"
-        when "ft3"
+        when "ft3", "fa1"
             "dr6"
         when "ft4"
             "dr8"
-        when "fa0"
-            "dr12"
+        when "ft5"
+            "dr10"
         else
             raise "Bad register #{name} for SH4 at #{codeOriginString}"