Ignore:
Timestamp:
Sep 10, 2015, 10:47:16 AM (10 years ago)
Author:
[email protected]
Message:

Add support for Callee-Saves registers
​https://bugs.webkit.org/show_bug.cgi?id=148666

Reviewed by Filip Pizlo.

We save platform callee save registers right below the call frame header,
in the location(s) starting with VirtualRegister 0. This local space is
allocated in the bytecode compiler. This space is the maximum space
needed for the callee registers that the LLInt and baseline JIT use,
rounded up to a stack aligned number of VirtualRegisters.
The LLInt explicitly saves and restores the registers in the macros
preserveCalleeSavesUsedByLLInt and restoreCalleeSavesUsedByLLInt.
The JITs saves and restores callee saves registers by what registers
are included in m_calleeSaveRegisters in the code block.

Added handling of callee save register restoration to exception handling.
The basic flow is when an exception is thrown or one is recognized to
have been generated in C++ code, we save the current state of all
callee save registers to VM::calleeSaveRegistersBuffer. As we unwind
looking for the corresponding catch, we copy the callee saves from call
frames to the same VM::calleeSaveRegistersBuffer. This is done for all
call frames on the stack up to but not including the call frame that has
the corresponding catch block. When we process the catch, we restore
the callee save registers with the contents of VM::calleeSaveRegistersBuffer.
If there isn't a catch, then handleUncaughtException will restore callee
saves before it returns back to the calling C++.

Eliminated callee saves registers as free registers for various thunk
generators as the callee saves may not have been saved by the function
calling the thunk.

Added code to transition callee saves from one VM's format to the another
as part of OSR entry and OSR exit.

Cleaned up the static RegisterSet's including adding one for LLInt and
baseline JIT callee saves and one to be used to allocate local registers
not including the callee saves or other special registers.

Moved ftl/FTLRegisterAtOffset.{cpp,h} to jit/RegisterAtOffset.{cpp,h}.
Factored out the vector of RegisterAtOffsets in ftl/FTLUnwindInfo.{cpp,h}
into a new class in jit/RegisterAtOffsetList.{cpp,h}.
Eliminted UnwindInfo and changed UnwindInfo::parse() into a standalone
function named parseUnwindInfo. That standalone function now returns
the callee saves RegisterAtOffsetList. This is stored in the CodeBlock
and used instead of UnwindInfo.

Turned off register preservation thunks for outgoing calls from FTL
generated code. THey'll be removed in a subsequent patch.

Changed specialized thinks to save and restore the contents of
tagTypeNumberRegister and tagMaskRegister as they can be called by FTL
compiled functions. We materialize those tag registers for the thunk's
use and then restore the prior contents on function exit.

Also removed the arity check fail return thunk since it is now the
caller's responsibility to restore the stack pointer.

Removed saving of callee save registers and materialization of special
tag registers for 64 bit platforms from vmEntryToJavaScript and
vmEntryToNative.

  • CMakeLists.txt:
  • JavaScriptCore.vcxproj/JavaScriptCore.vcxproj:
  • JavaScriptCore.vcxproj/JavaScriptCore.vcxproj.filters:
  • JavaScriptCore.xcodeproj/project.pbxproj:
  • ftl/FTLJITCode.h:
  • ftl/FTLRegisterAtOffset.cpp: Removed.
  • ftl/FTLRegisterAtOffset.h: Removed.
  • ftl/FTLUnwindInfo.cpp:

(JSC::FTL::parseUnwindInfo):
(JSC::FTL::UnwindInfo::UnwindInfo): Deleted.
(JSC::FTL::UnwindInfo::~UnwindInfo): Deleted.
(JSC::FTL::UnwindInfo::parse): Deleted.
(JSC::FTL::UnwindInfo::dump): Deleted.
(JSC::FTL::UnwindInfo::find): Deleted.
(JSC::FTL::UnwindInfo::indexOf): Deleted.

  • ftl/FTLUnwindInfo.h:

(JSC::RegisterAtOffset::dump):

  • jit/RegisterAtOffset.cpp: Added.
  • jit/RegisterAtOffset.h: Added.

(JSC::RegisterAtOffset::RegisterAtOffset):
(JSC::RegisterAtOffset::operator!):
(JSC::RegisterAtOffset::reg):
(JSC::RegisterAtOffset::offset):
(JSC::RegisterAtOffset::offsetAsIndex):
(JSC::RegisterAtOffset::operator==):
(JSC::RegisterAtOffset::operator<):
(JSC::RegisterAtOffset::getReg):

  • jit/RegisterAtOffsetList.cpp: Added.

(JSC::RegisterAtOffsetList::RegisterAtOffsetList):
(JSC::RegisterAtOffsetList::sort):
(JSC::RegisterAtOffsetList::dump):
(JSC::RegisterAtOffsetList::find):
(JSC::RegisterAtOffsetList::indexOf):

  • jit/RegisterAtOffsetList.h: Added.

(JSC::RegisterAtOffsetList::clear):
(JSC::RegisterAtOffsetList::size):
(JSC::RegisterAtOffsetList::at):
(JSC::RegisterAtOffsetList::append):
Move and refactored use of FTLRegisterAtOffset to RegisterAtOffset.
Added RegisterAtOffset and RegisterAtOffsetList to build configurations.
Remove FTLRegisterAtOffset files.

  • bytecode/CallLinkInfo.h:

(JSC::CallLinkInfo::setUpCallFromFTL):
Turned off FTL register preservation thunks.

  • bytecode/CodeBlock.cpp:

(JSC::CodeBlock::CodeBlock):
(JSC::CodeBlock::setCalleeSaveRegisters):
(JSC::roundCalleeSaveSpaceAsVirtualRegisters):
(JSC::CodeBlock::llintBaselineCalleeSaveSpaceAsVirtualRegisters):
(JSC::CodeBlock::calleeSaveSpaceAsVirtualRegisters):

  • bytecode/CodeBlock.h:

(JSC::CodeBlock::numberOfLLIntBaselineCalleeSaveRegisters):
(JSC::CodeBlock::calleeSaveRegisters):
(JSC::CodeBlock::llintBaselineCalleeSaveSpaceAsVirtualRegisters):
(JSC::CodeBlock::optimizeAfterWarmUp):
(JSC::CodeBlock::numberOfDFGCompiles):
Methods to manage a set of callee save registers. Also to allocate the appropriate
number of VirtualRegisters for callee saves.

  • bytecompiler/BytecodeGenerator.cpp:

(JSC::BytecodeGenerator::BytecodeGenerator):
(JSC::BytecodeGenerator::allocateCalleeSaveSpace):

  • bytecompiler/BytecodeGenerator.h:

Allocate the appropriate number of VirtualRegisters for callee saves needed by LLInt or baseline JIT.

  • dfg/DFGJITCompiler.cpp:

(JSC::DFG::JITCompiler::compileEntry):
(JSC::DFG::JITCompiler::compileSetupRegistersForEntry):
(JSC::DFG::JITCompiler::compileBody):
(JSC::DFG::JITCompiler::compileExceptionHandlers):
(JSC::DFG::JITCompiler::compile):
(JSC::DFG::JITCompiler::compileFunction):

  • dfg/DFGJITCompiler.h:
  • interpreter/Interpreter.cpp:

(JSC::UnwindFunctor::operator()):
(JSC::UnwindFunctor::copyCalleeSavesToVMCalleeSavesBuffer):

  • dfg/DFGPlan.cpp:

(JSC::DFG::Plan::compileInThreadImpl):

  • dfg/DFGSpeculativeJIT.cpp:

(JSC::DFG::SpeculativeJIT::usedRegisters):

  • dfg/DFGSpeculativeJIT32_64.cpp:

(JSC::DFG::SpeculativeJIT::compile):

  • dfg/DFGSpeculativeJIT64.cpp:

(JSC::DFG::SpeculativeJIT::compile):

  • dfg/DFGStackLayoutPhase.cpp:

(JSC::DFG::StackLayoutPhase::run):

  • ftl/FTLCompile.cpp:

(JSC::FTL::fixFunctionBasedOnStackMaps):
(JSC::FTL::compile):

  • ftl/FTLLink.cpp:

(JSC::FTL::link):

  • ftl/FTLOSRExitCompiler.cpp:

(JSC::FTL::compileStub):

  • ftl/FTLThunks.cpp:

(JSC::FTL::osrExitGenerationThunkGenerator):

  • jit/ArityCheckFailReturnThunks.cpp: Removed.
  • jit/ArityCheckFailReturnThunks.h: Removed.
  • jit/JIT.cpp:

(JSC::JIT::emitEnterOptimizationCheck):
(JSC::JIT::privateCompile):
(JSC::JIT::privateCompileExceptionHandlers):

  • jit/JITCall32_64.cpp:

(JSC::JIT::emit_op_ret):

  • jit/JITExceptions.cpp:

(JSC::genericUnwind):

  • jit/JITExceptions.h:
  • jit/JITOpcodes.cpp:

(JSC::JIT::emit_op_end):
(JSC::JIT::emit_op_ret):
(JSC::JIT::emit_op_throw):
(JSC::JIT::emit_op_catch):
(JSC::JIT::emit_op_enter):
(JSC::JIT::emitSlow_op_loop_hint):

  • jit/JITOpcodes32_64.cpp:

(JSC::JIT::emit_op_end):
(JSC::JIT::emit_op_throw):
(JSC::JIT::emit_op_catch):

  • jit/JITOperations.cpp:
  • jit/Repatch.cpp:

(JSC::generateByIdStub):

  • jit/ThunkGenerators.cpp:
  • llint/LLIntData.cpp:

(JSC::LLInt::Data::performAssertions):

  • llint/LLIntSlowPaths.cpp:

(JSC::LLInt::LLINT_SLOW_PATH_DECL):

  • llint/LowLevelInterpreter.asm:
  • llint/LowLevelInterpreter32_64.asm:
  • llint/LowLevelInterpreter64.asm:

(JSC::throwExceptionFromCallSlowPathGenerator):
(JSC::arityFixupGenerator):

  • runtime/CommonSlowPaths.cpp:

(JSC::setupArityCheckData):

  • runtime/CommonSlowPaths.h:

(JSC::CommonSlowPaths::arityCheckFor):
Emit code to save and restore callee save registers and materialize tagTypeNumberRegister
and tagMaskRegister.
Handle callee saves when tiering up.
Copy callee saves register contents to VM::calleeSaveRegistersBuffer at beginning of
exception processing.
Process callee save registers in frames when unwinding from an exception.
Restore callee saves register contents from VM::calleeSaveRegistersBuffer on catch.
Use appropriate register set to make sure we don't allocate a callee save register when
compiling a thunk.
Helper to populate tagTypeNumberRegister and tagMaskRegister with the appropriate
constants.
Removed arity fixup return thunks.

  • dfg/DFGOSREntry.cpp:

(JSC::DFG::prepareOSREntry):

  • dfg/DFGOSRExitCompiler32_64.cpp:

(JSC::DFG::OSRExitCompiler::compileExit):

  • dfg/DFGOSRExitCompiler64.cpp:

(JSC::DFG::OSRExitCompiler::compileExit):

  • dfg/DFGOSRExitCompilerCommon.cpp:

(JSC::DFG::reifyInlinedCallFrames):
(JSC::DFG::adjustAndJumpToTarget):
Restore callee saves from the DFG and save the appropriate ones for the baseline JIT.
Materialize the tag registers on 64 bit platforms.

  • jit/AssemblyHelpers.h:

(JSC::AssemblyHelpers::emitSaveCalleeSavesFor):
(JSC::AssemblyHelpers::emitRestoreCalleeSavesFor):
(JSC::AssemblyHelpers::emitSaveCalleeSaves):
(JSC::AssemblyHelpers::emitRestoreCalleeSaves):
(JSC::AssemblyHelpers::copyCalleeSavesToVMCalleeSavesBuffer):
(JSC::AssemblyHelpers::restoreCalleeSavesFromVMCalleeSavesBuffer):
(JSC::AssemblyHelpers::copyCalleeSavesFromFrameOrRegisterToVMCalleeSavesBuffer):
(JSC::AssemblyHelpers::emitMaterializeTagCheckRegisters):
New helpers to save and restore callee saves as well as materialize the tag registers
contents.

  • jit/FPRInfo.h:
  • jit/GPRInfo.h:

(JSC::GPRInfo::toRegister):
Updated to include FP callee save registers. Added number of callee saves registers and
cleanup register aliases that collide with callee save registers.

  • jit/JITPropertyAccess.cpp:

(JSC::JIT::emitGetByValWithCachedId):
(JSC::JIT::emitPutByValWithCachedId):
(JSC::JIT::emit_op_get_by_id):
(JSC::JIT::emit_op_put_by_id):

  • jit/JITPropertyAccess32_64.cpp:

(JSC::JIT::emitGetByValWithCachedId):
(JSC::JIT::emitPutByValWithCachedId):
(JSC::JIT::emit_op_get_by_id):
(JSC::JIT::emit_op_put_by_id):
Uses new stubUnavailableRegisters register set to limit what registers are available for
temporaries.

  • jit/RegisterSet.cpp:

(JSC::RegisterSet::stubUnavailableRegisters):
(JSC::RegisterSet::calleeSaveRegisters):
(JSC::RegisterSet::llintBaselineCalleeSaveRegisters):
(JSC::RegisterSet::dfgCalleeSaveRegisters):
(JSC::RegisterSet::ftlCalleeSaveRegisters):

  • jit/RegisterSet.h:

New register sets with the callee saves used by various tiers as well as one listing registers
not availble to stub code.

  • jit/SpecializedThunkJIT.h:

(JSC::SpecializedThunkJIT::SpecializedThunkJIT):
(JSC::SpecializedThunkJIT::loadDoubleArgument):
(JSC::SpecializedThunkJIT::returnJSValue):
(JSC::SpecializedThunkJIT::returnDouble):
(JSC::SpecializedThunkJIT::returnInt32):
(JSC::SpecializedThunkJIT::returnJSCell):
(JSC::SpecializedThunkJIT::callDoubleToDoublePreservingReturn):
(JSC::SpecializedThunkJIT::emitSaveThenMaterializeTagRegisters):
(JSC::SpecializedThunkJIT::emitRestoreSavedTagRegisters):
(JSC::SpecializedThunkJIT::tagReturnAsInt32):

  • jit/ThunkGenerators.cpp:

(JSC::nativeForGenerator):
Changed to save and restore existing tag register contents as the may contain other values.
After saving the existing values, we materialize the tag constants.

  • jit/TempRegisterSet.h:

(JSC::TempRegisterSet::getFPRByIndex):
(JSC::TempRegisterSet::getFreeFPR):
(JSC::TempRegisterSet::setByIndex):

  • offlineasm/arm64.rb:
  • offlineasm/registers.rb:

Added methods for floating point registers to support callee save FP registers.

  • jit/JITArithmetic32_64.cpp:

(JSC::JIT::emit_op_mod):
Removed unnecessary #if CPU(X86_64) check to this 32 bit only file.

  • offlineasm/x86.rb:

Fixed Windows callee saves naming.

  • runtime/VM.cpp:

(JSC::VM::VM):

  • runtime/VM.h:

(JSC::VM::calleeSaveRegistersBufferOffset):
(JSC::VM::getAllCalleeSaveRegistersMap):
Provide a RegisterSaveMap that has all registers that might be saved. Added a callee save buffer to be
used for OSR exit and for exception processing in a future patch.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/ftl/FTLUnwindInfo.cpp

    r177315 r189575  
    9595#include "FTLUnwindInfo.h"
    9696
     97#include "CodeBlock.h"
     98#include "RegisterAtOffsetList.h"
     99
    97100#if ENABLE(FTL_JIT)
    98101
    … …  
    103106
    104107namespace JSC { namespace FTL {
    105 
    106 UnwindInfo::UnwindInfo() { }
    107 UnwindInfo::~UnwindInfo() { }
    108 
    109108
    110109namespace {
    … …  
    655654} // anonymous namespace
    656655
    657 bool UnwindInfo::parse(void* section, size_t size, GeneratedFunction generatedFunction)
    658 {
    659     m_registers.clear();
     656std::unique_ptr<RegisterAtOffsetList> parseUnwindInfo(void* section, size_t size, GeneratedFunction generatedFunction)
     657{
    660658    RELEASE_ASSERT(!!section);
    661     if (!section)
    662         return false;
     659
     660    std::unique_ptr<RegisterAtOffsetList> registerOffsets = std::make_unique<RegisterAtOffsetList>();
    663661
    664662#if OS(DARWIN)
    … …  
    690688           
    691689        case UNWIND_X86_64_REG_RBX:
    692             m_registers.append(RegisterAtOffset(X86Registers::ebx, offset));
     690            registerOffsets->append(RegisterAtOffset(X86Registers::ebx, offset));
    693691            break;
    694692           
    695693        case UNWIND_X86_64_REG_R12:
    696             m_registers.append(RegisterAtOffset(X86Registers::r12, offset));
     694            registerOffsets->append(RegisterAtOffset(X86Registers::r12, offset));
    697695            break;
    698696           
    699697        case UNWIND_X86_64_REG_R13:
    700             m_registers.append(RegisterAtOffset(X86Registers::r13, offset));
     698            registerOffsets->append(RegisterAtOffset(X86Registers::r13, offset));
    701699            break;
    702700           
    703701        case UNWIND_X86_64_REG_R14:
    704             m_registers.append(RegisterAtOffset(X86Registers::r14, offset));
     702            registerOffsets->append(RegisterAtOffset(X86Registers::r14, offset));
    705703            break;
    706704           
    707705        case UNWIND_X86_64_REG_R15:
    708             m_registers.append(RegisterAtOffset(X86Registers::r15, offset));
     706            registerOffsets->append(RegisterAtOffset(X86Registers::r15, offset));
    709707            break;
    710708           
    711709        case UNWIND_X86_64_REG_RBP:
    712             m_registers.append(RegisterAtOffset(X86Registers::ebp, offset));
     710            registerOffsets->append(RegisterAtOffset(X86Registers::ebp, offset));
    713711            break;
    714712           
    … …  
    722720    RELEASE_ASSERT((encoding & UNWIND_ARM64_MODE_MASK) == UNWIND_ARM64_MODE_FRAME);
    723721   
    724     m_registers.append(RegisterAtOffset(ARM64Registers::fp, 0));
     722    registerOffsets->append(RegisterAtOffset(ARM64Registers::fp, 0));
    725723   
    726724    int32_t offset = 0;
    727725    if (encoding & UNWIND_ARM64_FRAME_X19_X20_PAIR) {
    728         m_registers.append(RegisterAtOffset(ARM64Registers::x19, offset -= 8));
    729         m_registers.append(RegisterAtOffset(ARM64Registers::x20, offset -= 8));
     726        registerOffsets->append(RegisterAtOffset(ARM64Registers::x19, offset -= 8));
     727        registerOffsets->append(RegisterAtOffset(ARM64Registers::x20, offset -= 8));
    730728    }
    731729    if (encoding & UNWIND_ARM64_FRAME_X21_X22_PAIR) {
    732         m_registers.append(RegisterAtOffset(ARM64Registers::x21, offset -= 8));
    733         m_registers.append(RegisterAtOffset(ARM64Registers::x22, offset -= 8));
     730        registerOffsets->append(RegisterAtOffset(ARM64Registers::x21, offset -= 8));
     731        registerOffsets->append(RegisterAtOffset(ARM64Registers::x22, offset -= 8));
    734732    }
    735733    if (encoding & UNWIND_ARM64_FRAME_X23_X24_PAIR) {
    736         m_registers.append(RegisterAtOffset(ARM64Registers::x23, offset -= 8));
    737         m_registers.append(RegisterAtOffset(ARM64Registers::x24, offset -= 8));
     734        registerOffsets->append(RegisterAtOffset(ARM64Registers::x23, offset -= 8));
     735        registerOffsets->append(RegisterAtOffset(ARM64Registers::x24, offset -= 8));
    738736    }
    739737    if (encoding & UNWIND_ARM64_FRAME_X25_X26_PAIR) {
    740         m_registers.append(RegisterAtOffset(ARM64Registers::x25, offset -= 8));
    741         m_registers.append(RegisterAtOffset(ARM64Registers::x26, offset -= 8));
     738        registerOffsets->append(RegisterAtOffset(ARM64Registers::x25, offset -= 8));
     739        registerOffsets->append(RegisterAtOffset(ARM64Registers::x26, offset -= 8));
    742740    }
    743741    if (encoding & UNWIND_ARM64_FRAME_X27_X28_PAIR) {
    744         m_registers.append(RegisterAtOffset(ARM64Registers::x27, offset -= 8));
    745         m_registers.append(RegisterAtOffset(ARM64Registers::x28, offset -= 8));
     742        registerOffsets->append(RegisterAtOffset(ARM64Registers::x27, offset -= 8));
     743        registerOffsets->append(RegisterAtOffset(ARM64Registers::x28, offset -= 8));
    746744    }
    747745    if (encoding & UNWIND_ARM64_FRAME_D8_D9_PAIR) {
    748         m_registers.append(RegisterAtOffset(ARM64Registers::q8, offset -= 8));
    749         m_registers.append(RegisterAtOffset(ARM64Registers::q9, offset -= 8));
     746        registerOffsets->append(RegisterAtOffset(ARM64Registers::q8, offset -= 8));
     747        registerOffsets->append(RegisterAtOffset(ARM64Registers::q9, offset -= 8));
    750748    }
    751749    if (encoding & UNWIND_ARM64_FRAME_D10_D11_PAIR) {
    752         m_registers.append(RegisterAtOffset(ARM64Registers::q10, offset -= 8));
    753         m_registers.append(RegisterAtOffset(ARM64Registers::q11, offset -= 8));
     750        registerOffsets->append(RegisterAtOffset(ARM64Registers::q10, offset -= 8));
     751        registerOffsets->append(RegisterAtOffset(ARM64Registers::q11, offset -= 8));
    754752    }
    755753    if (encoding & UNWIND_ARM64_FRAME_D12_D13_PAIR) {
    756         m_registers.append(RegisterAtOffset(ARM64Registers::q12, offset -= 8));
    757         m_registers.append(RegisterAtOffset(ARM64Registers::q13, offset -= 8));
     754        registerOffsets->append(RegisterAtOffset(ARM64Registers::q12, offset -= 8));
     755        registerOffsets->append(RegisterAtOffset(ARM64Registers::q13, offset -= 8));
    758756    }
    759757    if (encoding & UNWIND_ARM64_FRAME_D14_D15_PAIR) {
    760         m_registers.append(RegisterAtOffset(ARM64Registers::q14, offset -= 8));
    761         m_registers.append(RegisterAtOffset(ARM64Registers::q15, offset -= 8));
     758        registerOffsets->append(RegisterAtOffset(ARM64Registers::q14, offset -= 8));
     759        registerOffsets->append(RegisterAtOffset(ARM64Registers::q15, offset -= 8));
    762760    }
    763761#else
    … …  
    783781            switch (i) {
    784782            case UNW_X86_64_rbx:
    785                 m_registers.append(RegisterAtOffset(X86Registers::ebx, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     783                registerOffsets->append(RegisterAtOffset(X86Registers::ebx, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    786784                break;
    787785            case UNW_X86_64_r12:
    788                 m_registers.append(RegisterAtOffset(X86Registers::r12, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     786                registerOffsets->append(RegisterAtOffset(X86Registers::r12, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    789787                break;
    790788            case UNW_X86_64_r13:
    791                 m_registers.append(RegisterAtOffset(X86Registers::r13, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     789                registerOffsets->append(RegisterAtOffset(X86Registers::r13, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    792790                break;
    793791            case UNW_X86_64_r14:
    794                 m_registers.append(RegisterAtOffset(X86Registers::r14, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     792                registerOffsets->append(RegisterAtOffset(X86Registers::r14, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    795793                break;
    796794            case UNW_X86_64_r15:
    797                 m_registers.append(RegisterAtOffset(X86Registers::r15, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     795                registerOffsets->append(RegisterAtOffset(X86Registers::r15, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    798796                break;
    799797            case UNW_X86_64_rbp:
    800                 m_registers.append(RegisterAtOffset(X86Registers::ebp, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     798                registerOffsets->append(RegisterAtOffset(X86Registers::ebp, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    801799                break;
    802800            case DW_X86_64_RET_addr:
    … …  
    817815            switch (i) {
    818816            case UNW_ARM64_x0:
    819                 m_registers.append(RegisterAtOffset(ARM64Registers::x0, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     817                registerOffsets->append(RegisterAtOffset(ARM64Registers::x0, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    820818                break;
    821819            case UNW_ARM64_x1:
    822                 m_registers.append(RegisterAtOffset(ARM64Registers::x1, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     820                registerOffsets->append(RegisterAtOffset(ARM64Registers::x1, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    823821                break;
    824822            case UNW_ARM64_x2:
    825                 m_registers.append(RegisterAtOffset(ARM64Registers::x2, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     823                registerOffsets->append(RegisterAtOffset(ARM64Registers::x2, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    826824                break;
    827825            case UNW_ARM64_x3:
    828                 m_registers.append(RegisterAtOffset(ARM64Registers::x3, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     826                registerOffsets->append(RegisterAtOffset(ARM64Registers::x3, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    829827                break;
    830828            case UNW_ARM64_x4:
    831                 m_registers.append(RegisterAtOffset(ARM64Registers::x4, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     829                registerOffsets->append(RegisterAtOffset(ARM64Registers::x4, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    832830                break;
    833831            case UNW_ARM64_x5:
    834                 m_registers.append(RegisterAtOffset(ARM64Registers::x5, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     832                registerOffsets->append(RegisterAtOffset(ARM64Registers::x5, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    835833                break;
    836834            case UNW_ARM64_x6:
    837                 m_registers.append(RegisterAtOffset(ARM64Registers::x6, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     835                registerOffsets->append(RegisterAtOffset(ARM64Registers::x6, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    838836                break;
    839837            case UNW_ARM64_x7:
    840                 m_registers.append(RegisterAtOffset(ARM64Registers::x7, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     838                registerOffsets->append(RegisterAtOffset(ARM64Registers::x7, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    841839                break;
    842840            case UNW_ARM64_x8:
    843                 m_registers.append(RegisterAtOffset(ARM64Registers::x8, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     841                registerOffsets->append(RegisterAtOffset(ARM64Registers::x8, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    844842                break;
    845843            case UNW_ARM64_x9:
    846                 m_registers.append(RegisterAtOffset(ARM64Registers::x9, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     844                registerOffsets->append(RegisterAtOffset(ARM64Registers::x9, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    847845                break;
    848846            case UNW_ARM64_x10:
    849                 m_registers.append(RegisterAtOffset(ARM64Registers::x10, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     847                registerOffsets->append(RegisterAtOffset(ARM64Registers::x10, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    850848                break;
    851849            case UNW_ARM64_x11:
    852                 m_registers.append(RegisterAtOffset(ARM64Registers::x11, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     850                registerOffsets->append(RegisterAtOffset(ARM64Registers::x11, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    853851                break;
    854852            case UNW_ARM64_x12:
    855                 m_registers.append(RegisterAtOffset(ARM64Registers::x12, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     853                registerOffsets->append(RegisterAtOffset(ARM64Registers::x12, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    856854                break;
    857855            case UNW_ARM64_x13:
    858                 m_registers.append(RegisterAtOffset(ARM64Registers::x13, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     856                registerOffsets->append(RegisterAtOffset(ARM64Registers::x13, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    859857                break;
    860858            case UNW_ARM64_x14:
    861                 m_registers.append(RegisterAtOffset(ARM64Registers::x14, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     859                registerOffsets->append(RegisterAtOffset(ARM64Registers::x14, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    862860                break;
    863861            case UNW_ARM64_x15:
    864                 m_registers.append(RegisterAtOffset(ARM64Registers::x15, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     862                registerOffsets->append(RegisterAtOffset(ARM64Registers::x15, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    865863                break;
    866864            case UNW_ARM64_x16:
    867                 m_registers.append(RegisterAtOffset(ARM64Registers::x16, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     865                registerOffsets->append(RegisterAtOffset(ARM64Registers::x16, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    868866                break;
    869867            case UNW_ARM64_x17:
    870                 m_registers.append(RegisterAtOffset(ARM64Registers::x17, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     868                registerOffsets->append(RegisterAtOffset(ARM64Registers::x17, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    871869                break;
    872870            case UNW_ARM64_x18:
    873                 m_registers.append(RegisterAtOffset(ARM64Registers::x18, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     871                registerOffsets->append(RegisterAtOffset(ARM64Registers::x18, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    874872                break;
    875873            case UNW_ARM64_x19:
    876                 m_registers.append(RegisterAtOffset(ARM64Registers::x19, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     874                registerOffsets->append(RegisterAtOffset(ARM64Registers::x19, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    877875                break;
    878876            case UNW_ARM64_x20:
    879                 m_registers.append(RegisterAtOffset(ARM64Registers::x20, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     877                registerOffsets->append(RegisterAtOffset(ARM64Registers::x20, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    880878                break;
    881879            case UNW_ARM64_x21:
    882                 m_registers.append(RegisterAtOffset(ARM64Registers::x21, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     880                registerOffsets->append(RegisterAtOffset(ARM64Registers::x21, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    883881                break;
    884882            case UNW_ARM64_x22:
    885                 m_registers.append(RegisterAtOffset(ARM64Registers::x22, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     883                registerOffsets->append(RegisterAtOffset(ARM64Registers::x22, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    886884                break;
    887885            case UNW_ARM64_x23:
    888                 m_registers.append(RegisterAtOffset(ARM64Registers::x23, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     886                registerOffsets->append(RegisterAtOffset(ARM64Registers::x23, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    889887                break;
    890888            case UNW_ARM64_x24:
    891                 m_registers.append(RegisterAtOffset(ARM64Registers::x24, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     889                registerOffsets->append(RegisterAtOffset(ARM64Registers::x24, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    892890                break;
    893891            case UNW_ARM64_x25:
    894                 m_registers.append(RegisterAtOffset(ARM64Registers::x25, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     892                registerOffsets->append(RegisterAtOffset(ARM64Registers::x25, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    895893                break;
    896894            case UNW_ARM64_x26:
    897                 m_registers.append(RegisterAtOffset(ARM64Registers::x26, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     895                registerOffsets->append(RegisterAtOffset(ARM64Registers::x26, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    898896                break;
    899897            case UNW_ARM64_x27:
    900                 m_registers.append(RegisterAtOffset(ARM64Registers::x27, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     898                registerOffsets->append(RegisterAtOffset(ARM64Registers::x27, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    901899                break;
    902900            case UNW_ARM64_x28:
    903                 m_registers.append(RegisterAtOffset(ARM64Registers::x28, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     901                registerOffsets->append(RegisterAtOffset(ARM64Registers::x28, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    904902                break;
    905903            case UNW_ARM64_fp:
    906                 m_registers.append(RegisterAtOffset(ARM64Registers::fp, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     904                registerOffsets->append(RegisterAtOffset(ARM64Registers::fp, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    907905                break;
    908906            case UNW_ARM64_x30:
    909                 m_registers.append(RegisterAtOffset(ARM64Registers::x30, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     907                registerOffsets->append(RegisterAtOffset(ARM64Registers::x30, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    910908                break;
    911909            case UNW_ARM64_sp:
    912                 m_registers.append(RegisterAtOffset(ARM64Registers::sp, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     910                registerOffsets->append(RegisterAtOffset(ARM64Registers::sp, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    913911                break;
    914912            case UNW_ARM64_v0:
    915                 m_registers.append(RegisterAtOffset(ARM64Registers::q0, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     913                registerOffsets->append(RegisterAtOffset(ARM64Registers::q0, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    916914                break;
    917915            case UNW_ARM64_v1:
    918                 m_registers.append(RegisterAtOffset(ARM64Registers::q1, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     916                registerOffsets->append(RegisterAtOffset(ARM64Registers::q1, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    919917                break;
    920918            case UNW_ARM64_v2:
    921                 m_registers.append(RegisterAtOffset(ARM64Registers::q2, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     919                registerOffsets->append(RegisterAtOffset(ARM64Registers::q2, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    922920                break;
    923921            case UNW_ARM64_v3:
    924                 m_registers.append(RegisterAtOffset(ARM64Registers::q3, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     922                registerOffsets->append(RegisterAtOffset(ARM64Registers::q3, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    925923                break;
    926924            case UNW_ARM64_v4:
    927                 m_registers.append(RegisterAtOffset(ARM64Registers::q4, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     925                registerOffsets->append(RegisterAtOffset(ARM64Registers::q4, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    928926                break;
    929927            case UNW_ARM64_v5:
    930                 m_registers.append(RegisterAtOffset(ARM64Registers::q5, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     928                registerOffsets->append(RegisterAtOffset(ARM64Registers::q5, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    931929                break;
    932930            case UNW_ARM64_v6:
    933                 m_registers.append(RegisterAtOffset(ARM64Registers::q6, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     931                registerOffsets->append(RegisterAtOffset(ARM64Registers::q6, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    934932                break;
    935933            case UNW_ARM64_v7:
    936                 m_registers.append(RegisterAtOffset(ARM64Registers::q7, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     934                registerOffsets->append(RegisterAtOffset(ARM64Registers::q7, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    937935                break;
    938936            case UNW_ARM64_v8:
    939                 m_registers.append(RegisterAtOffset(ARM64Registers::q8, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     937                registerOffsets->append(RegisterAtOffset(ARM64Registers::q8, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    940938                break;
    941939            case UNW_ARM64_v9:
    942                 m_registers.append(RegisterAtOffset(ARM64Registers::q9, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     940                registerOffsets->append(RegisterAtOffset(ARM64Registers::q9, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    943941                break;
    944942            case UNW_ARM64_v10:
    945                 m_registers.append(RegisterAtOffset(ARM64Registers::q10, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     943                registerOffsets->append(RegisterAtOffset(ARM64Registers::q10, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    946944                break;
    947945            case UNW_ARM64_v11:
    948                 m_registers.append(RegisterAtOffset(ARM64Registers::q11, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     946                registerOffsets->append(RegisterAtOffset(ARM64Registers::q11, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    949947                break;
    950948            case UNW_ARM64_v12:
    951                 m_registers.append(RegisterAtOffset(ARM64Registers::q12, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     949                registerOffsets->append(RegisterAtOffset(ARM64Registers::q12, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    952950                break;
    953951            case UNW_ARM64_v13:
    954                 m_registers.append(RegisterAtOffset(ARM64Registers::q13, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     952                registerOffsets->append(RegisterAtOffset(ARM64Registers::q13, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    955953                break;
    956954            case UNW_ARM64_v14:
    957                 m_registers.append(RegisterAtOffset(ARM64Registers::q14, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     955                registerOffsets->append(RegisterAtOffset(ARM64Registers::q14, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    958956                break;
    959957            case UNW_ARM64_v15:
    960                 m_registers.append(RegisterAtOffset(ARM64Registers::q15, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     958                registerOffsets->append(RegisterAtOffset(ARM64Registers::q15, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    961959                break;
    962960            case UNW_ARM64_v16:
    963                 m_registers.append(RegisterAtOffset(ARM64Registers::q16, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     961                registerOffsets->append(RegisterAtOffset(ARM64Registers::q16, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    964962                break;
    965963            case UNW_ARM64_v17:
    966                 m_registers.append(RegisterAtOffset(ARM64Registers::q17, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     964                registerOffsets->append(RegisterAtOffset(ARM64Registers::q17, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    967965                break;
    968966            case UNW_ARM64_v18:
    969                 m_registers.append(RegisterAtOffset(ARM64Registers::q18, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     967                registerOffsets->append(RegisterAtOffset(ARM64Registers::q18, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    970968                break;
    971969            case UNW_ARM64_v19:
    972                 m_registers.append(RegisterAtOffset(ARM64Registers::q19, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     970                registerOffsets->append(RegisterAtOffset(ARM64Registers::q19, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    973971                break;
    974972            case UNW_ARM64_v20:
    975                 m_registers.append(RegisterAtOffset(ARM64Registers::q20, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     973                registerOffsets->append(RegisterAtOffset(ARM64Registers::q20, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    976974                break;
    977975            case UNW_ARM64_v21:
    978                 m_registers.append(RegisterAtOffset(ARM64Registers::q21, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     976                append(RegisterAtOffset(ARM64Registers::q21, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    979977                break;
    980978            case UNW_ARM64_v22:
    981                 m_registers.append(RegisterAtOffset(ARM64Registers::q22, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     979                registerOffsets->append(RegisterAtOffset(ARM64Registers::q22, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    982980                break;
    983981            case UNW_ARM64_v23:
    984                 m_registers.append(RegisterAtOffset(ARM64Registers::q23, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     982                registerOffsets->append(RegisterAtOffset(ARM64Registers::q23, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    985983                break;
    986984            case UNW_ARM64_v24:
    987                 m_registers.append(RegisterAtOffset(ARM64Registers::q24, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     985                registerOffsets->append(RegisterAtOffset(ARM64Registers::q24, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    988986                break;
    989987            case UNW_ARM64_v25:
    990                 m_registers.append(RegisterAtOffset(ARM64Registers::q25, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     988                registerOffsets->append(RegisterAtOffset(ARM64Registers::q25, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    991989                break;
    992990            case UNW_ARM64_v26:
    993                 m_registers.append(RegisterAtOffset(ARM64Registers::q26, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     991                registerOffsets->append(RegisterAtOffset(ARM64Registers::q26, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    994992                break;
    995993            case UNW_ARM64_v27:
    996                 m_registers.append(RegisterAtOffset(ARM64Registers::q27, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     994                registerOffsets->append(RegisterAtOffset(ARM64Registers::q27, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    997995                break;
    998996            case UNW_ARM64_v28:
    999                 m_registers.append(RegisterAtOffset(ARM64Registers::q28, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     997                registerOffsets->append(RegisterAtOffset(ARM64Registers::q28, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    1000998                break;
    1001999            case UNW_ARM64_v29:
    1002                 m_registers.append(RegisterAtOffset(ARM64Registers::q29, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     1000                registerOffsets->append(RegisterAtOffset(ARM64Registers::q29, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    10031001                break;
    10041002            case UNW_ARM64_v30:
    1005                 m_registers.append(RegisterAtOffset(ARM64Registers::q30, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     1003                registerOffsets->append(RegisterAtOffset(ARM64Registers::q30, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    10061004                break;
    10071005            case UNW_ARM64_v31:
    1008                 m_registers.append(RegisterAtOffset(ARM64Registers::q31, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
     1006                registerOffsets->append(RegisterAtOffset(ARM64Registers::q31, prolog.savedRegisters[i].offset + prolog.cfaRegisterOffset));
    10091007                break;
    10101008            default:
    … …  
    10181016
    10191017#endif
    1020     std::sort(m_registers.begin(), m_registers.end());
    1021     return true;
    1022 }
    1023 
    1024 void UnwindInfo::dump(PrintStream& out) const
    1025 {
    1026     out.print(listDump(m_registers));
    1027 }
    1028 
    1029 RegisterAtOffset* UnwindInfo::find(Reg reg) const
    1030 {
    1031     return tryBinarySearch<RegisterAtOffset, Reg>(m_registers, m_registers.size(), reg, RegisterAtOffset::getReg);
    1032 }
    1033 
    1034 unsigned UnwindInfo::indexOf(Reg reg) const
    1035 {
    1036     if (RegisterAtOffset* pointer = find(reg))
    1037         return pointer - m_registers.begin();
    1038     return UINT_MAX;
     1018    registerOffsets->sort();
     1019    return WTF::move(registerOffsets);
    10391020}
    10401021
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