Ignore:
Timestamp:
Mar 10, 2017, 9:49:42 AM (8 years ago)
Author:
[email protected]
Message:

B3 should have comprehensive support for atomic operations
​https://bugs.webkit.org/show_bug.cgi?id=162349

Reviewed by Keith Miller.

Source/JavaScriptCore:

This adds the following capabilities to B3:

  • Atomic weak/strong unfenced/fenced compare-and-swap
  • Atomic add/sub/or/and/xor/xchg
  • Acquire/release fencing on loads/stores
  • Fenceless load-load dependencies


This adds lowering to the following instructions on x86:

  • lock cmpxchg
  • lock xadd
  • lock add/sub/or/and/xor/xchg


This adds lowering to the following instructions on ARM64:

  • ldar and friends
  • stlr and friends
  • ldxr and friends (unfenced LL)
  • stxr and friends (unfended SC)
  • ldaxr and friends (fenced LL)
  • stlxr and friends (fenced SC)
  • eor as a fenceless load-load dependency


This does instruction selection pattern matching to ensure that weak/strong CAS and all of the
variants of fences and atomic math ops get lowered to the best possible instruction sequence.
For example, we support the Equal(AtomicStrongCAS(expected, ...), expected) pattern and a bunch
of its friends. You can say Branch(Equal(AtomicStrongCAS(expected, ...), expected)) and it will
generate the best possible branch sequence on x86 and ARM64.

B3 now knows how to model all of the kinds of fencing. It knows that acq loads are ordered with
respect to each other and with respect to rel stores, creating sequential consistency that
transcends just the acq/rel fences themselves (see Effects::fence). It knows that the phantom
fence effects may only target some abstract heaps but not others, so that load elimination and
store sinking can still operate across fences if you just tell B3 that the fence does not alias
those accesses. This makes it super easy to teach B3 that some of your heap is thread-local.
Even better, it lets you express fine-grained dependencies where the atomics that affect one
property in shared memory do not clobber non-atomics that ffect some other property in shared
memory.

One of my favorite features is Depend, which allows you to express load-load dependencies. On
x86 it lowers to nothing, while on ARM64 it lowers to eor.

This also exposes a common atomicWeakCAS API to the x86_64/ARM64 MacroAssemblers. Same for
acq/rel. JSC's 64-bit JITs are now a happy concurrency playground.

This doesn't yet expose the functionality to JS or wasm. SAB still uses the non-intrinsic
implementations of the Atomics object, for now.

  • CMakeLists.txt:
  • JavaScriptCore.xcodeproj/project.pbxproj:
  • assembler/ARM64Assembler.h:

(JSC::ARM64Assembler::ldar):
(JSC::ARM64Assembler::ldxr):
(JSC::ARM64Assembler::ldaxr):
(JSC::ARM64Assembler::stxr):
(JSC::ARM64Assembler::stlr):
(JSC::ARM64Assembler::stlxr):
(JSC::ARM64Assembler::excepnGenerationImmMask):
(JSC::ARM64Assembler::exoticLoad):
(JSC::ARM64Assembler::storeRelease):
(JSC::ARM64Assembler::exoticStore):

  • assembler/AbstractMacroAssembler.cpp: Added.

(WTF::printInternal):

  • assembler/AbstractMacroAssembler.h:

(JSC::AbstractMacroAssemblerBase::invert):

  • assembler/MacroAssembler.h:
  • assembler/MacroAssemblerARM64.h:

(JSC::MacroAssemblerARM64::loadAcq8SignedExtendTo32):
(JSC::MacroAssemblerARM64::loadAcq8):
(JSC::MacroAssemblerARM64::storeRel8):
(JSC::MacroAssemblerARM64::loadAcq16SignedExtendTo32):
(JSC::MacroAssemblerARM64::loadAcq16):
(JSC::MacroAssemblerARM64::storeRel16):
(JSC::MacroAssemblerARM64::loadAcq32):
(JSC::MacroAssemblerARM64::loadAcq64):
(JSC::MacroAssemblerARM64::storeRel32):
(JSC::MacroAssemblerARM64::storeRel64):
(JSC::MacroAssemblerARM64::loadLink8):
(JSC::MacroAssemblerARM64::loadLinkAcq8):
(JSC::MacroAssemblerARM64::storeCond8):
(JSC::MacroAssemblerARM64::storeCondRel8):
(JSC::MacroAssemblerARM64::loadLink16):
(JSC::MacroAssemblerARM64::loadLinkAcq16):
(JSC::MacroAssemblerARM64::storeCond16):
(JSC::MacroAssemblerARM64::storeCondRel16):
(JSC::MacroAssemblerARM64::loadLink32):
(JSC::MacroAssemblerARM64::loadLinkAcq32):
(JSC::MacroAssemblerARM64::storeCond32):
(JSC::MacroAssemblerARM64::storeCondRel32):
(JSC::MacroAssemblerARM64::loadLink64):
(JSC::MacroAssemblerARM64::loadLinkAcq64):
(JSC::MacroAssemblerARM64::storeCond64):
(JSC::MacroAssemblerARM64::storeCondRel64):
(JSC::MacroAssemblerARM64::atomicStrongCAS8):
(JSC::MacroAssemblerARM64::atomicStrongCAS16):
(JSC::MacroAssemblerARM64::atomicStrongCAS32):
(JSC::MacroAssemblerARM64::atomicStrongCAS64):
(JSC::MacroAssemblerARM64::atomicRelaxedStrongCAS8):
(JSC::MacroAssemblerARM64::atomicRelaxedStrongCAS16):
(JSC::MacroAssemblerARM64::atomicRelaxedStrongCAS32):
(JSC::MacroAssemblerARM64::atomicRelaxedStrongCAS64):
(JSC::MacroAssemblerARM64::branchAtomicWeakCAS8):
(JSC::MacroAssemblerARM64::branchAtomicWeakCAS16):
(JSC::MacroAssemblerARM64::branchAtomicWeakCAS32):
(JSC::MacroAssemblerARM64::branchAtomicWeakCAS64):
(JSC::MacroAssemblerARM64::branchAtomicRelaxedWeakCAS8):
(JSC::MacroAssemblerARM64::branchAtomicRelaxedWeakCAS16):
(JSC::MacroAssemblerARM64::branchAtomicRelaxedWeakCAS32):
(JSC::MacroAssemblerARM64::branchAtomicRelaxedWeakCAS64):
(JSC::MacroAssemblerARM64::depend32):
(JSC::MacroAssemblerARM64::depend64):
(JSC::MacroAssemblerARM64::loadLink):
(JSC::MacroAssemblerARM64::loadLinkAcq):
(JSC::MacroAssemblerARM64::storeCond):
(JSC::MacroAssemblerARM64::storeCondRel):
(JSC::MacroAssemblerARM64::signExtend):
(JSC::MacroAssemblerARM64::branch):
(JSC::MacroAssemblerARM64::atomicStrongCAS):
(JSC::MacroAssemblerARM64::atomicRelaxedStrongCAS):
(JSC::MacroAssemblerARM64::branchAtomicWeakCAS):
(JSC::MacroAssemblerARM64::branchAtomicRelaxedWeakCAS):
(JSC::MacroAssemblerARM64::extractSimpleAddress):
(JSC::MacroAssemblerARM64::signExtend<8>):
(JSC::MacroAssemblerARM64::signExtend<16>):
(JSC::MacroAssemblerARM64::branch<64>):

  • assembler/MacroAssemblerX86Common.h:

(JSC::MacroAssemblerX86Common::add32):
(JSC::MacroAssemblerX86Common::and32):
(JSC::MacroAssemblerX86Common::and16):
(JSC::MacroAssemblerX86Common::and8):
(JSC::MacroAssemblerX86Common::neg32):
(JSC::MacroAssemblerX86Common::neg16):
(JSC::MacroAssemblerX86Common::neg8):
(JSC::MacroAssemblerX86Common::or32):
(JSC::MacroAssemblerX86Common::or16):
(JSC::MacroAssemblerX86Common::or8):
(JSC::MacroAssemblerX86Common::sub16):
(JSC::MacroAssemblerX86Common::sub8):
(JSC::MacroAssemblerX86Common::sub32):
(JSC::MacroAssemblerX86Common::xor32):
(JSC::MacroAssemblerX86Common::xor16):
(JSC::MacroAssemblerX86Common::xor8):
(JSC::MacroAssemblerX86Common::not32):
(JSC::MacroAssemblerX86Common::not16):
(JSC::MacroAssemblerX86Common::not8):
(JSC::MacroAssemblerX86Common::store16):
(JSC::MacroAssemblerX86Common::atomicStrongCAS8):
(JSC::MacroAssemblerX86Common::atomicStrongCAS16):
(JSC::MacroAssemblerX86Common::atomicStrongCAS32):
(JSC::MacroAssemblerX86Common::branchAtomicStrongCAS8):
(JSC::MacroAssemblerX86Common::branchAtomicStrongCAS16):
(JSC::MacroAssemblerX86Common::branchAtomicStrongCAS32):
(JSC::MacroAssemblerX86Common::atomicWeakCAS8):
(JSC::MacroAssemblerX86Common::atomicWeakCAS16):
(JSC::MacroAssemblerX86Common::atomicWeakCAS32):
(JSC::MacroAssemblerX86Common::branchAtomicWeakCAS8):
(JSC::MacroAssemblerX86Common::branchAtomicWeakCAS16):
(JSC::MacroAssemblerX86Common::branchAtomicWeakCAS32):
(JSC::MacroAssemblerX86Common::atomicRelaxedWeakCAS8):
(JSC::MacroAssemblerX86Common::atomicRelaxedWeakCAS16):
(JSC::MacroAssemblerX86Common::atomicRelaxedWeakCAS32):
(JSC::MacroAssemblerX86Common::branchAtomicRelaxedWeakCAS8):
(JSC::MacroAssemblerX86Common::branchAtomicRelaxedWeakCAS16):
(JSC::MacroAssemblerX86Common::branchAtomicRelaxedWeakCAS32):
(JSC::MacroAssemblerX86Common::atomicAdd8):
(JSC::MacroAssemblerX86Common::atomicAdd16):
(JSC::MacroAssemblerX86Common::atomicAdd32):
(JSC::MacroAssemblerX86Common::atomicSub8):
(JSC::MacroAssemblerX86Common::atomicSub16):
(JSC::MacroAssemblerX86Common::atomicSub32):
(JSC::MacroAssemblerX86Common::atomicAnd8):
(JSC::MacroAssemblerX86Common::atomicAnd16):
(JSC::MacroAssemblerX86Common::atomicAnd32):
(JSC::MacroAssemblerX86Common::atomicOr8):
(JSC::MacroAssemblerX86Common::atomicOr16):
(JSC::MacroAssemblerX86Common::atomicOr32):
(JSC::MacroAssemblerX86Common::atomicXor8):
(JSC::MacroAssemblerX86Common::atomicXor16):
(JSC::MacroAssemblerX86Common::atomicXor32):
(JSC::MacroAssemblerX86Common::atomicNeg8):
(JSC::MacroAssemblerX86Common::atomicNeg16):
(JSC::MacroAssemblerX86Common::atomicNeg32):
(JSC::MacroAssemblerX86Common::atomicNot8):
(JSC::MacroAssemblerX86Common::atomicNot16):
(JSC::MacroAssemblerX86Common::atomicNot32):
(JSC::MacroAssemblerX86Common::atomicXchgAdd8):
(JSC::MacroAssemblerX86Common::atomicXchgAdd16):
(JSC::MacroAssemblerX86Common::atomicXchgAdd32):
(JSC::MacroAssemblerX86Common::atomicXchg8):
(JSC::MacroAssemblerX86Common::atomicXchg16):
(JSC::MacroAssemblerX86Common::atomicXchg32):
(JSC::MacroAssemblerX86Common::loadAcq8):
(JSC::MacroAssemblerX86Common::loadAcq8SignedExtendTo32):
(JSC::MacroAssemblerX86Common::loadAcq16):
(JSC::MacroAssemblerX86Common::loadAcq16SignedExtendTo32):
(JSC::MacroAssemblerX86Common::loadAcq32):
(JSC::MacroAssemblerX86Common::storeRel8):
(JSC::MacroAssemblerX86Common::storeRel16):
(JSC::MacroAssemblerX86Common::storeRel32):
(JSC::MacroAssemblerX86Common::storeFence):
(JSC::MacroAssemblerX86Common::loadFence):
(JSC::MacroAssemblerX86Common::replaceWithJump):
(JSC::MacroAssemblerX86Common::maxJumpReplacementSize):
(JSC::MacroAssemblerX86Common::patchableJumpSize):
(JSC::MacroAssemblerX86Common::supportsFloatingPointRounding):
(JSC::MacroAssemblerX86Common::supportsAVX):
(JSC::MacroAssemblerX86Common::updateEax1EcxFlags):
(JSC::MacroAssemblerX86Common::x86Condition):
(JSC::MacroAssemblerX86Common::atomicStrongCAS):
(JSC::MacroAssemblerX86Common::branchAtomicStrongCAS):

  • assembler/MacroAssemblerX86_64.h:

(JSC::MacroAssemblerX86_64::add64):
(JSC::MacroAssemblerX86_64::and64):
(JSC::MacroAssemblerX86_64::neg64):
(JSC::MacroAssemblerX86_64::or64):
(JSC::MacroAssemblerX86_64::sub64):
(JSC::MacroAssemblerX86_64::xor64):
(JSC::MacroAssemblerX86_64::not64):
(JSC::MacroAssemblerX86_64::store64):
(JSC::MacroAssemblerX86_64::atomicStrongCAS64):
(JSC::MacroAssemblerX86_64::branchAtomicStrongCAS64):
(JSC::MacroAssemblerX86_64::atomicWeakCAS64):
(JSC::MacroAssemblerX86_64::branchAtomicWeakCAS64):
(JSC::MacroAssemblerX86_64::atomicRelaxedWeakCAS64):
(JSC::MacroAssemblerX86_64::branchAtomicRelaxedWeakCAS64):
(JSC::MacroAssemblerX86_64::atomicAdd64):
(JSC::MacroAssemblerX86_64::atomicSub64):
(JSC::MacroAssemblerX86_64::atomicAnd64):
(JSC::MacroAssemblerX86_64::atomicOr64):
(JSC::MacroAssemblerX86_64::atomicXor64):
(JSC::MacroAssemblerX86_64::atomicNeg64):
(JSC::MacroAssemblerX86_64::atomicNot64):
(JSC::MacroAssemblerX86_64::atomicXchgAdd64):
(JSC::MacroAssemblerX86_64::atomicXchg64):
(JSC::MacroAssemblerX86_64::loadAcq64):
(JSC::MacroAssemblerX86_64::storeRel64):

  • assembler/X86Assembler.h:

(JSC::X86Assembler::addl_mr):
(JSC::X86Assembler::addq_mr):
(JSC::X86Assembler::addq_rm):
(JSC::X86Assembler::addq_im):
(JSC::X86Assembler::andl_mr):
(JSC::X86Assembler::andl_rm):
(JSC::X86Assembler::andw_rm):
(JSC::X86Assembler::andb_rm):
(JSC::X86Assembler::andl_im):
(JSC::X86Assembler::andw_im):
(JSC::X86Assembler::andb_im):
(JSC::X86Assembler::andq_mr):
(JSC::X86Assembler::andq_rm):
(JSC::X86Assembler::andq_im):
(JSC::X86Assembler::incq_m):
(JSC::X86Assembler::negq_m):
(JSC::X86Assembler::negl_m):
(JSC::X86Assembler::negw_m):
(JSC::X86Assembler::negb_m):
(JSC::X86Assembler::notl_m):
(JSC::X86Assembler::notw_m):
(JSC::X86Assembler::notb_m):
(JSC::X86Assembler::notq_m):
(JSC::X86Assembler::orl_mr):
(JSC::X86Assembler::orl_rm):
(JSC::X86Assembler::orw_rm):
(JSC::X86Assembler::orb_rm):
(JSC::X86Assembler::orl_im):
(JSC::X86Assembler::orw_im):
(JSC::X86Assembler::orb_im):
(JSC::X86Assembler::orq_mr):
(JSC::X86Assembler::orq_rm):
(JSC::X86Assembler::orq_im):
(JSC::X86Assembler::subl_mr):
(JSC::X86Assembler::subl_rm):
(JSC::X86Assembler::subw_rm):
(JSC::X86Assembler::subb_rm):
(JSC::X86Assembler::subl_im):
(JSC::X86Assembler::subw_im):
(JSC::X86Assembler::subb_im):
(JSC::X86Assembler::subq_mr):
(JSC::X86Assembler::subq_rm):
(JSC::X86Assembler::subq_im):
(JSC::X86Assembler::xorl_mr):
(JSC::X86Assembler::xorl_rm):
(JSC::X86Assembler::xorl_im):
(JSC::X86Assembler::xorw_rm):
(JSC::X86Assembler::xorw_im):
(JSC::X86Assembler::xorb_rm):
(JSC::X86Assembler::xorb_im):
(JSC::X86Assembler::xorq_im):
(JSC::X86Assembler::xorq_rm):
(JSC::X86Assembler::xorq_mr):
(JSC::X86Assembler::xchgb_rm):
(JSC::X86Assembler::xchgw_rm):
(JSC::X86Assembler::xchgl_rm):
(JSC::X86Assembler::xchgq_rm):
(JSC::X86Assembler::movw_im):
(JSC::X86Assembler::movq_i32m):
(JSC::X86Assembler::cmpxchgb_rm):
(JSC::X86Assembler::cmpxchgw_rm):
(JSC::X86Assembler::cmpxchgl_rm):
(JSC::X86Assembler::cmpxchgq_rm):
(JSC::X86Assembler::xaddb_rm):
(JSC::X86Assembler::xaddw_rm):
(JSC::X86Assembler::xaddl_rm):
(JSC::X86Assembler::xaddq_rm):
(JSC::X86Assembler::X86InstructionFormatter::SingleInstructionBufferWriter::memoryModRM):

  • b3/B3AtomicValue.cpp: Added.

(JSC::B3::AtomicValue::~AtomicValue):
(JSC::B3::AtomicValue::dumpMeta):
(JSC::B3::AtomicValue::cloneImpl):
(JSC::B3::AtomicValue::AtomicValue):

  • b3/B3AtomicValue.h: Added.
  • b3/B3BasicBlock.h:
  • b3/B3BlockInsertionSet.cpp:

(JSC::B3::BlockInsertionSet::BlockInsertionSet):
(JSC::B3::BlockInsertionSet::insert): Deleted.
(JSC::B3::BlockInsertionSet::insertBefore): Deleted.
(JSC::B3::BlockInsertionSet::insertAfter): Deleted.
(JSC::B3::BlockInsertionSet::execute): Deleted.

  • b3/B3BlockInsertionSet.h:
  • b3/B3Effects.cpp:

(JSC::B3::Effects::interferes):
(JSC::B3::Effects::operator==):
(JSC::B3::Effects::dump):

  • b3/B3Effects.h:

(JSC::B3::Effects::forCall):
(JSC::B3::Effects::mustExecute):

  • b3/B3EliminateCommonSubexpressions.cpp:
  • b3/B3Generate.cpp:

(JSC::B3::generateToAir):

  • b3/B3GenericBlockInsertionSet.h: Added.

(JSC::B3::GenericBlockInsertionSet::GenericBlockInsertionSet):
(JSC::B3::GenericBlockInsertionSet::insert):
(JSC::B3::GenericBlockInsertionSet::insertBefore):
(JSC::B3::GenericBlockInsertionSet::insertAfter):
(JSC::B3::GenericBlockInsertionSet::execute):

  • b3/B3HeapRange.h:

(JSC::B3::HeapRange::operator|):

  • b3/B3InsertionSet.cpp:

(JSC::B3::InsertionSet::insertClone):

  • b3/B3InsertionSet.h:
  • b3/B3LegalizeMemoryOffsets.cpp:
  • b3/B3LowerMacros.cpp:

(JSC::B3::lowerMacros):

  • b3/B3LowerMacrosAfterOptimizations.cpp:
  • b3/B3LowerToAir.cpp:

(JSC::B3::Air::LowerToAir::LowerToAir):
(JSC::B3::Air::LowerToAir::run):
(JSC::B3::Air::LowerToAir::effectiveAddr):
(JSC::B3::Air::LowerToAir::addr):
(JSC::B3::Air::LowerToAir::loadPromiseAnyOpcode):
(JSC::B3::Air::LowerToAir::appendShift):
(JSC::B3::Air::LowerToAir::tryAppendStoreBinOp):
(JSC::B3::Air::LowerToAir::storeOpcode):
(JSC::B3::Air::LowerToAir::createStore):
(JSC::B3::Air::LowerToAir::finishAppendingInstructions):
(JSC::B3::Air::LowerToAir::newBlock):
(JSC::B3::Air::LowerToAir::splitBlock):
(JSC::B3::Air::LowerToAir::fillStackmap):
(JSC::B3::Air::LowerToAir::appendX86Div):
(JSC::B3::Air::LowerToAir::appendX86UDiv):
(JSC::B3::Air::LowerToAir::loadLinkOpcode):
(JSC::B3::Air::LowerToAir::storeCondOpcode):
(JSC::B3::Air::LowerToAir::appendCAS):
(JSC::B3::Air::LowerToAir::appendVoidAtomic):
(JSC::B3::Air::LowerToAir::appendGeneralAtomic):
(JSC::B3::Air::LowerToAir::lower):
(JSC::B3::Air::LowerToAir::lowerX86Div): Deleted.
(JSC::B3::Air::LowerToAir::lowerX86UDiv): Deleted.

  • b3/B3LowerToAir.h:
  • b3/B3MemoryValue.cpp:

(JSC::B3::MemoryValue::isLegalOffset):
(JSC::B3::MemoryValue::accessType):
(JSC::B3::MemoryValue::accessBank):
(JSC::B3::MemoryValue::accessByteSize):
(JSC::B3::MemoryValue::dumpMeta):
(JSC::B3::MemoryValue::MemoryValue):
(JSC::B3::MemoryValue::accessWidth): Deleted.

  • b3/B3MemoryValue.h:
  • b3/B3MemoryValueInlines.h: Added.

(JSC::B3::MemoryValue::isLegalOffset):
(JSC::B3::MemoryValue::requiresSimpleAddr):
(JSC::B3::MemoryValue::accessWidth):

  • b3/B3MoveConstants.cpp:
  • b3/B3NativeTraits.h: Added.
  • b3/B3Opcode.cpp:

(JSC::B3::storeOpcode):
(WTF::printInternal):

  • b3/B3Opcode.h:

(JSC::B3::isLoad):
(JSC::B3::isStore):
(JSC::B3::isLoadStore):
(JSC::B3::isAtomic):
(JSC::B3::isAtomicCAS):
(JSC::B3::isAtomicXchg):
(JSC::B3::isMemoryAccess):
(JSC::B3::signExtendOpcode):

  • b3/B3Procedure.cpp:

(JSC::B3::Procedure::dump):

  • b3/B3Procedure.h:

(JSC::B3::Procedure::hasQuirks):
(JSC::B3::Procedure::setHasQuirks):

  • b3/B3PureCSE.cpp:

(JSC::B3::pureCSE):

  • b3/B3PureCSE.h:
  • b3/B3ReduceStrength.cpp:
  • b3/B3Validate.cpp:
  • b3/B3Value.cpp:

(JSC::B3::Value::returnsBool):
(JSC::B3::Value::effects):
(JSC::B3::Value::key):
(JSC::B3::Value::performSubstitution):
(JSC::B3::Value::typeFor):

  • b3/B3Value.h:
  • b3/B3Width.cpp:

(JSC::B3::bestType):

  • b3/B3Width.h:

(JSC::B3::canonicalWidth):
(JSC::B3::isCanonicalWidth):
(JSC::B3::mask):

  • b3/air/AirArg.cpp:

(JSC::B3::Air::Arg::jsHash):
(JSC::B3::Air::Arg::dump):
(WTF::printInternal):

  • b3/air/AirArg.h:

(JSC::B3::Air::Arg::isAnyUse):
(JSC::B3::Air::Arg::isColdUse):
(JSC::B3::Air::Arg::cooled):
(JSC::B3::Air::Arg::isEarlyUse):
(JSC::B3::Air::Arg::isLateUse):
(JSC::B3::Air::Arg::isAnyDef):
(JSC::B3::Air::Arg::isEarlyDef):
(JSC::B3::Air::Arg::isLateDef):
(JSC::B3::Air::Arg::isZDef):
(JSC::B3::Air::Arg::simpleAddr):
(JSC::B3::Air::Arg::statusCond):
(JSC::B3::Air::Arg::isSimpleAddr):
(JSC::B3::Air::Arg::isMemory):
(JSC::B3::Air::Arg::isStatusCond):
(JSC::B3::Air::Arg::isCondition):
(JSC::B3::Air::Arg::ptr):
(JSC::B3::Air::Arg::base):
(JSC::B3::Air::Arg::isGP):
(JSC::B3::Air::Arg::isFP):
(JSC::B3::Air::Arg::isValidForm):
(JSC::B3::Air::Arg::forEachTmpFast):
(JSC::B3::Air::Arg::forEachTmp):
(JSC::B3::Air::Arg::asAddress):
(JSC::B3::Air::Arg::asStatusCondition):
(JSC::B3::Air::Arg::isInvertible):
(JSC::B3::Air::Arg::inverted):

  • b3/air/AirBasicBlock.cpp:

(JSC::B3::Air::BasicBlock::setSuccessors):

  • b3/air/AirBasicBlock.h:
  • b3/air/AirBlockInsertionSet.cpp: Added.

(JSC::B3::Air::BlockInsertionSet::BlockInsertionSet):
(JSC::B3::Air::BlockInsertionSet::~BlockInsertionSet):

  • b3/air/AirBlockInsertionSet.h: Added.
  • b3/air/AirDumpAsJS.cpp: Removed.
  • b3/air/AirDumpAsJS.h: Removed.
  • b3/air/AirEliminateDeadCode.cpp:

(JSC::B3::Air::eliminateDeadCode):

  • b3/air/AirGenerate.cpp:

(JSC::B3::Air::prepareForGeneration):

  • b3/air/AirInstInlines.h:

(JSC::B3::Air::isAtomicStrongCASValid):
(JSC::B3::Air::isBranchAtomicStrongCASValid):
(JSC::B3::Air::isAtomicStrongCAS8Valid):
(JSC::B3::Air::isAtomicStrongCAS16Valid):
(JSC::B3::Air::isAtomicStrongCAS32Valid):
(JSC::B3::Air::isAtomicStrongCAS64Valid):
(JSC::B3::Air::isBranchAtomicStrongCAS8Valid):
(JSC::B3::Air::isBranchAtomicStrongCAS16Valid):
(JSC::B3::Air::isBranchAtomicStrongCAS32Valid):
(JSC::B3::Air::isBranchAtomicStrongCAS64Valid):

  • b3/air/AirOpcode.opcodes:
  • b3/air/AirOptimizeBlockOrder.cpp:

(JSC::B3::Air::optimizeBlockOrder):

  • b3/air/AirPadInterference.cpp:

(JSC::B3::Air::padInterference):

  • b3/air/AirSpillEverything.cpp:

(JSC::B3::Air::spillEverything):

  • b3/air/opcode_generator.rb:
  • b3/testb3.cpp:

(JSC::B3::testLoadAcq42):
(JSC::B3::testStoreRelAddLoadAcq32):
(JSC::B3::testStoreRelAddLoadAcq8):
(JSC::B3::testStoreRelAddFenceLoadAcq8):
(JSC::B3::testStoreRelAddLoadAcq16):
(JSC::B3::testStoreRelAddLoadAcq64):
(JSC::B3::testTrappingStoreElimination):
(JSC::B3::testX86LeaAddAdd):
(JSC::B3::testX86LeaAddShlLeftScale1):
(JSC::B3::testAtomicWeakCAS):
(JSC::B3::testAtomicStrongCAS):
(JSC::B3::testAtomicXchg):
(JSC::B3::testDepend32):
(JSC::B3::testDepend64):
(JSC::B3::run):

  • runtime/Options.h:

Websites/webkit.org:

Document the new opcodes!

  • docs/b3/intermediate-representation.html:
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/assembler/MacroAssemblerX86Common.h

    r213652 r213714  
    172172    }
    173173
     174    void add32(BaseIndex src, RegisterID dest)
     175    {
     176        m_assembler.addl_mr(src.offset, src.base, src.index, src.scale, dest);
     177    }
     178
    174179    void add32(RegisterID src, Address dest)
    175180    {
    … …  
    252257    }
    253258
     259    void and32(RegisterID src, BaseIndex dest)
     260    {
     261        m_assembler.andl_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     262    }
     263
     264    void and16(RegisterID src, Address dest)
     265    {
     266        m_assembler.andw_rm(src, dest.offset, dest.base);
     267    }
     268
     269    void and16(RegisterID src, BaseIndex dest)
     270    {
     271        m_assembler.andw_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     272    }
     273
     274    void and8(RegisterID src, Address dest)
     275    {
     276        m_assembler.andb_rm(src, dest.offset, dest.base);
     277    }
     278
     279    void and8(RegisterID src, BaseIndex dest)
     280    {
     281        m_assembler.andb_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     282    }
     283
    254284    void and32(Address src, RegisterID dest)
    255285    {
    … …  
    257287    }
    258288
     289    void and32(BaseIndex src, RegisterID dest)
     290    {
     291        m_assembler.andl_mr(src.offset, src.base, src.index, src.scale, dest);
     292    }
     293
    259294    void and32(TrustedImm32 imm, Address address)
    260295    {
    261296        m_assembler.andl_im(imm.m_value, address.offset, address.base);
     297    }
     298
     299    void and32(TrustedImm32 imm, BaseIndex address)
     300    {
     301        m_assembler.andl_im(imm.m_value, address.offset, address.base, address.index, address.scale);
     302    }
     303
     304    void and16(TrustedImm32 imm, Address address)
     305    {
     306        m_assembler.andw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base);
     307    }
     308
     309    void and16(TrustedImm32 imm, BaseIndex address)
     310    {
     311        m_assembler.andw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
     312    }
     313
     314    void and8(TrustedImm32 imm, Address address)
     315    {
     316        m_assembler.andb_im(static_cast<int8_t>(imm.m_value), address.offset, address.base);
     317    }
     318
     319    void and8(TrustedImm32 imm, BaseIndex address)
     320    {
     321        m_assembler.andb_im(static_cast<int8_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
    262322    }
    263323
    … …  
    457517    }
    458518
     519    void neg32(BaseIndex srcDest)
     520    {
     521        m_assembler.negl_m(srcDest.offset, srcDest.base, srcDest.index, srcDest.scale);
     522    }
     523
     524    void neg16(Address srcDest)
     525    {
     526        m_assembler.negw_m(srcDest.offset, srcDest.base);
     527    }
     528
     529    void neg16(BaseIndex srcDest)
     530    {
     531        m_assembler.negw_m(srcDest.offset, srcDest.base, srcDest.index, srcDest.scale);
     532    }
     533
     534    void neg8(Address srcDest)
     535    {
     536        m_assembler.negb_m(srcDest.offset, srcDest.base);
     537    }
     538
     539    void neg8(BaseIndex srcDest)
     540    {
     541        m_assembler.negb_m(srcDest.offset, srcDest.base, srcDest.index, srcDest.scale);
     542    }
     543
    459544    void or32(RegisterID src, RegisterID dest)
    460545    {
    … …  
    472557    }
    473558
     559    void or32(RegisterID src, BaseIndex dest)
     560    {
     561        m_assembler.orl_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     562    }
     563
     564    void or16(RegisterID src, Address dest)
     565    {
     566        m_assembler.orw_rm(src, dest.offset, dest.base);
     567    }
     568
     569    void or16(RegisterID src, BaseIndex dest)
     570    {
     571        m_assembler.orw_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     572    }
     573
     574    void or8(RegisterID src, Address dest)
     575    {
     576        m_assembler.orb_rm(src, dest.offset, dest.base);
     577    }
     578
     579    void or8(RegisterID src, BaseIndex dest)
     580    {
     581        m_assembler.orb_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     582    }
     583
    474584    void or32(Address src, RegisterID dest)
    475585    {
    … …  
    477587    }
    478588
     589    void or32(BaseIndex src, RegisterID dest)
     590    {
     591        m_assembler.orl_mr(src.offset, src.base, src.index, src.scale, dest);
     592    }
     593
    479594    void or32(TrustedImm32 imm, Address address)
    480595    {
    481596        m_assembler.orl_im(imm.m_value, address.offset, address.base);
     597    }
     598
     599    void or32(TrustedImm32 imm, BaseIndex address)
     600    {
     601        m_assembler.orl_im(imm.m_value, address.offset, address.base, address.index, address.scale);
     602    }
     603
     604    void or16(TrustedImm32 imm, Address address)
     605    {
     606        m_assembler.orw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base);
     607    }
     608
     609    void or16(TrustedImm32 imm, BaseIndex address)
     610    {
     611        m_assembler.orw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
     612    }
     613
     614    void or8(TrustedImm32 imm, Address address)
     615    {
     616        m_assembler.orb_im(static_cast<int8_t>(imm.m_value), address.offset, address.base);
     617    }
     618
     619    void or8(TrustedImm32 imm, BaseIndex address)
     620    {
     621        m_assembler.orb_im(static_cast<int8_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
    482622    }
    483623
    … …  
    655795    }
    656796
     797    void sub16(TrustedImm32 imm, Address address)
     798    {
     799        m_assembler.subw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base);
     800    }
     801
     802    void sub8(TrustedImm32 imm, Address address)
     803    {
     804        m_assembler.subb_im(static_cast<int8_t>(imm.m_value), address.offset, address.base);
     805    }
     806
     807    void sub32(TrustedImm32 imm, BaseIndex address)
     808    {
     809        m_assembler.subl_im(imm.m_value, address.offset, address.base, address.index, address.scale);
     810    }
     811
     812    void sub16(TrustedImm32 imm, BaseIndex address)
     813    {
     814        m_assembler.subw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
     815    }
     816
     817    void sub8(TrustedImm32 imm, BaseIndex address)
     818    {
     819        m_assembler.subb_im(static_cast<int8_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
     820    }
     821
    657822    void sub32(Address src, RegisterID dest)
    658823    {
    … …  
    660825    }
    661826
     827    void sub32(BaseIndex src, RegisterID dest)
     828    {
     829        m_assembler.subl_mr(src.offset, src.base, src.index, src.scale, dest);
     830    }
     831
    662832    void sub32(RegisterID src, Address dest)
    663833    {
    664834        m_assembler.subl_rm(src, dest.offset, dest.base);
     835    }
     836
     837    void sub16(RegisterID src, Address dest)
     838    {
     839        m_assembler.subw_rm(src, dest.offset, dest.base);
     840    }
     841
     842    void sub8(RegisterID src, Address dest)
     843    {
     844        m_assembler.subb_rm(src, dest.offset, dest.base);
     845    }
     846
     847    void sub32(RegisterID src, BaseIndex dest)
     848    {
     849        m_assembler.subl_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     850    }
     851
     852    void sub16(RegisterID src, BaseIndex dest)
     853    {
     854        m_assembler.subw_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     855    }
     856
     857    void sub8(RegisterID src, BaseIndex dest)
     858    {
     859        m_assembler.subb_rm(src, dest.offset, dest.base, dest.index, dest.scale);
    665860    }
    666861
    … …  
    678873    }
    679874
     875    void xor32(TrustedImm32 imm, BaseIndex dest)
     876    {
     877        if (imm.m_value == -1)
     878            m_assembler.notl_m(dest.offset, dest.base, dest.index, dest.scale);
     879        else
     880            m_assembler.xorl_im(imm.m_value, dest.offset, dest.base, dest.index, dest.scale);
     881    }
     882
     883    void xor16(TrustedImm32 imm, Address dest)
     884    {
     885        imm.m_value = static_cast<int16_t>(imm.m_value);
     886        if (imm.m_value == -1)
     887            m_assembler.notw_m(dest.offset, dest.base);
     888        else
     889            m_assembler.xorw_im(imm.m_value, dest.offset, dest.base);
     890    }
     891
     892    void xor16(TrustedImm32 imm, BaseIndex dest)
     893    {
     894        imm.m_value = static_cast<int16_t>(imm.m_value);
     895        if (imm.m_value == -1)
     896            m_assembler.notw_m(dest.offset, dest.base, dest.index, dest.scale);
     897        else
     898            m_assembler.xorw_im(imm.m_value, dest.offset, dest.base, dest.index, dest.scale);
     899    }
     900
     901    void xor8(TrustedImm32 imm, Address dest)
     902    {
     903        imm.m_value = static_cast<int8_t>(imm.m_value);
     904        if (imm.m_value == -1)
     905            m_assembler.notb_m(dest.offset, dest.base);
     906        else
     907            m_assembler.xorb_im(imm.m_value, dest.offset, dest.base);
     908    }
     909
     910    void xor8(TrustedImm32 imm, BaseIndex dest)
     911    {
     912        imm.m_value = static_cast<int8_t>(imm.m_value);
     913        if (imm.m_value == -1)
     914            m_assembler.notb_m(dest.offset, dest.base, dest.index, dest.scale);
     915        else
     916            m_assembler.xorb_im(imm.m_value, dest.offset, dest.base, dest.index, dest.scale);
     917    }
     918
    680919    void xor32(TrustedImm32 imm, RegisterID dest)
    681920    {
    … …  
    691930    }
    692931
     932    void xor32(RegisterID src, BaseIndex dest)
     933    {
     934        m_assembler.xorl_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     935    }
     936
     937    void xor16(RegisterID src, Address dest)
     938    {
     939        m_assembler.xorw_rm(src, dest.offset, dest.base);
     940    }
     941
     942    void xor16(RegisterID src, BaseIndex dest)
     943    {
     944        m_assembler.xorw_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     945    }
     946
     947    void xor8(RegisterID src, Address dest)
     948    {
     949        m_assembler.xorb_rm(src, dest.offset, dest.base);
     950    }
     951
     952    void xor8(RegisterID src, BaseIndex dest)
     953    {
     954        m_assembler.xorb_rm(src, dest.offset, dest.base, dest.index, dest.scale);
     955    }
     956
    693957    void xor32(Address src, RegisterID dest)
    694958    {
    695959        m_assembler.xorl_mr(src.offset, src.base, dest);
     960    }
     961   
     962    void xor32(BaseIndex src, RegisterID dest)
     963    {
     964        m_assembler.xorl_mr(src.offset, src.base, src.index, src.scale, dest);
    696965    }
    697966   
    … …  
    7421011    }
    7431012
     1013    void not32(BaseIndex dest)
     1014    {
     1015        m_assembler.notl_m(dest.offset, dest.base, dest.index, dest.scale);
     1016    }
     1017
     1018    void not16(Address dest)
     1019    {
     1020        m_assembler.notw_m(dest.offset, dest.base);
     1021    }
     1022
     1023    void not16(BaseIndex dest)
     1024    {
     1025        m_assembler.notw_m(dest.offset, dest.base, dest.index, dest.scale);
     1026    }
     1027
     1028    void not8(Address dest)
     1029    {
     1030        m_assembler.notb_m(dest.offset, dest.base);
     1031    }
     1032
     1033    void not8(BaseIndex dest)
     1034    {
     1035        m_assembler.notb_m(dest.offset, dest.base, dest.index, dest.scale);
     1036    }
     1037
    7441038    void sqrtDouble(FPRegisterID src, FPRegisterID dst)
    7451039    {
    … …  
    10721366    void store16(RegisterID src, BaseIndex address)
    10731367    {
    1074 #if CPU(X86)
    1075         // On 32-bit x86 we can only store from the first 4 registers;
    1076         // esp..edi are mapped to the 'h' registers!
    1077         if (src >= 4) {
    1078             // Pick a temporary register.
    1079             RegisterID temp = getUnusedRegister(address);
    1080 
    1081             // Swap to the temporary register to perform the store.
    1082             swap(src, temp);
    1083             m_assembler.movw_rm(temp, address.offset, address.base, address.index, address.scale);
    1084             swap(src, temp);
    1085             return;
    1086         }
    1087 #endif
    10881368        m_assembler.movw_rm(src, address.offset, address.base, address.index, address.scale);
    10891369    }
    … …  
    10911371    void store16(RegisterID src, Address address)
    10921372    {
    1093 #if CPU(X86)
    1094         // On 32-bit x86 we can only store from the first 4 registers;
    1095         // esp..edi are mapped to the 'h' registers!
    1096         if (src >= 4) {
    1097             // Pick a temporary register.
    1098             RegisterID temp = getUnusedRegister(address);
    1099 
    1100             // Swap to the temporary register to perform the store.
    1101             swap(src, temp);
    1102             m_assembler.movw_rm(temp, address.offset, address.base);
    1103             swap(src, temp);
    1104             return;
    1105         }
    1106 #endif
    11071373        m_assembler.movw_rm(src, address.offset, address.base);
    11081374    }
    11091375
     1376    void store16(TrustedImm32 imm, BaseIndex address)
     1377    {
     1378        m_assembler.movw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base, address.index, address.scale);
     1379    }
     1380
     1381    void store16(TrustedImm32 imm, Address address)
     1382    {
     1383        m_assembler.movw_im(static_cast<int16_t>(imm.m_value), address.offset, address.base);
     1384    }
    11101385
    11111386    // Floating-point operation:
    … …  
    27463021        m_assembler.orl_im(0, 0, X86Registers::esp);
    27473022    }
    2748 
     3023   
     3024    void atomicStrongCAS8(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, Address address, RegisterID result)
     3025    {
     3026        atomicStrongCAS(cond, expectedAndResult, result, [&] { m_assembler.cmpxchgb_rm(newValue, address.offset, address.base); });
     3027    }
     3028
     3029    void atomicStrongCAS8(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, BaseIndex address, RegisterID result)
     3030    {
     3031        atomicStrongCAS(cond, expectedAndResult, result, [&] { m_assembler.cmpxchgb_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3032    }
     3033
     3034    void atomicStrongCAS16(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, Address address, RegisterID result)
     3035    {
     3036        atomicStrongCAS(cond, expectedAndResult, result, [&] { m_assembler.cmpxchgw_rm(newValue, address.offset, address.base); });
     3037    }
     3038
     3039    void atomicStrongCAS16(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, BaseIndex address, RegisterID result)
     3040    {
     3041        atomicStrongCAS(cond, expectedAndResult, result, [&] { m_assembler.cmpxchgw_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3042    }
     3043
     3044    void atomicStrongCAS32(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, Address address, RegisterID result)
     3045    {
     3046        atomicStrongCAS(cond, expectedAndResult, result, [&] { m_assembler.cmpxchgl_rm(newValue, address.offset, address.base); });
     3047    }
     3048
     3049    void atomicStrongCAS32(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, BaseIndex address, RegisterID result)
     3050    {
     3051        atomicStrongCAS(cond, expectedAndResult, result, [&] { m_assembler.cmpxchgl_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3052    }
     3053
     3054    void atomicStrongCAS8(RegisterID expectedAndResult, RegisterID newValue, Address address)
     3055    {
     3056        atomicStrongCAS(expectedAndResult, [&] { m_assembler.cmpxchgb_rm(newValue, address.offset, address.base); });
     3057    }
     3058
     3059    void atomicStrongCAS8(RegisterID expectedAndResult, RegisterID newValue, BaseIndex address)
     3060    {
     3061        atomicStrongCAS(expectedAndResult, [&] { m_assembler.cmpxchgb_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3062    }
     3063
     3064    void atomicStrongCAS16(RegisterID expectedAndResult, RegisterID newValue, Address address)
     3065    {
     3066        atomicStrongCAS(expectedAndResult, [&] { m_assembler.cmpxchgw_rm(newValue, address.offset, address.base); });
     3067    }
     3068
     3069    void atomicStrongCAS16(RegisterID expectedAndResult, RegisterID newValue, BaseIndex address)
     3070    {
     3071        atomicStrongCAS(expectedAndResult, [&] { m_assembler.cmpxchgw_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3072    }
     3073
     3074    void atomicStrongCAS32(RegisterID expectedAndResult, RegisterID newValue, Address address)
     3075    {
     3076        atomicStrongCAS(expectedAndResult, [&] { m_assembler.cmpxchgl_rm(newValue, address.offset, address.base); });
     3077    }
     3078
     3079    void atomicStrongCAS32(RegisterID expectedAndResult, RegisterID newValue, BaseIndex address)
     3080    {
     3081        atomicStrongCAS(expectedAndResult, [&] { m_assembler.cmpxchgl_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3082    }
     3083
     3084    Jump branchAtomicStrongCAS8(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, Address address)
     3085    {
     3086        return branchAtomicStrongCAS(cond, expectedAndResult, [&] { m_assembler.cmpxchgb_rm(newValue, address.offset, address.base); });
     3087    }
     3088
     3089    Jump branchAtomicStrongCAS8(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, BaseIndex address)
     3090    {
     3091        return branchAtomicStrongCAS(cond, expectedAndResult, [&] { m_assembler.cmpxchgb_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3092    }
     3093
     3094    Jump branchAtomicStrongCAS16(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, Address address)
     3095    {
     3096        return branchAtomicStrongCAS(cond, expectedAndResult, [&] { m_assembler.cmpxchgw_rm(newValue, address.offset, address.base); });
     3097    }
     3098
     3099    Jump branchAtomicStrongCAS16(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, BaseIndex address)
     3100    {
     3101        return branchAtomicStrongCAS(cond, expectedAndResult, [&] { m_assembler.cmpxchgw_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3102    }
     3103
     3104    Jump branchAtomicStrongCAS32(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, Address address)
     3105    {
     3106        return branchAtomicStrongCAS(cond, expectedAndResult, [&] { m_assembler.cmpxchgl_rm(newValue, address.offset, address.base); });
     3107    }
     3108
     3109    Jump branchAtomicStrongCAS32(StatusCondition cond, RegisterID expectedAndResult, RegisterID newValue, BaseIndex address)
     3110    {
     3111        return branchAtomicStrongCAS(cond, expectedAndResult, [&] { m_assembler.cmpxchgl_rm(newValue, address.offset, address.base, address.index, address.scale); });
     3112    }
     3113
     3114    // If you use weak CAS, you cannot rely on expectedAndClobbered to have any particular value after
     3115    // this completes. On x86, it will contain the result of the strong CAS. On ARM, it will still have
     3116    // the expected value.
     3117    void atomicWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address, RegisterID result)
     3118    {
     3119        atomicStrongCAS8(cond, expectedAndClobbered, newValue, address, result);
     3120    }
     3121
     3122    void atomicWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address, RegisterID result)
     3123    {
     3124        atomicStrongCAS8(cond, expectedAndClobbered, newValue, address, result);
     3125    }
     3126
     3127    void atomicWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address, RegisterID result)
     3128    {
     3129        atomicStrongCAS16(cond, expectedAndClobbered, newValue, address, result);
     3130    }
     3131
     3132    void atomicWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address, RegisterID result)
     3133    {
     3134        atomicStrongCAS16(cond, expectedAndClobbered, newValue, address, result);
     3135    }
     3136
     3137    void atomicWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address, RegisterID result)
     3138    {
     3139        atomicStrongCAS32(cond, expectedAndClobbered, newValue, address, result);
     3140    }
     3141
     3142    void atomicWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address, RegisterID result)
     3143    {
     3144        atomicStrongCAS32(cond, expectedAndClobbered, newValue, address, result);
     3145    }
     3146
     3147    Jump branchAtomicWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address)
     3148    {
     3149        return branchAtomicStrongCAS8(cond, expectedAndClobbered, newValue, address);
     3150    }
     3151
     3152    Jump branchAtomicWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address)
     3153    {
     3154        return branchAtomicStrongCAS8(cond, expectedAndClobbered, newValue, address);
     3155    }
     3156
     3157    Jump branchAtomicWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address)
     3158    {
     3159        return branchAtomicStrongCAS16(cond, expectedAndClobbered, newValue, address);
     3160    }
     3161
     3162    Jump branchAtomicWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address)
     3163    {
     3164        return branchAtomicStrongCAS16(cond, expectedAndClobbered, newValue, address);
     3165    }
     3166
     3167    Jump branchAtomicWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address)
     3168    {
     3169        return branchAtomicStrongCAS32(cond, expectedAndClobbered, newValue, address);
     3170    }
     3171
     3172    Jump branchAtomicWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address)
     3173    {
     3174        return branchAtomicStrongCAS32(cond, expectedAndClobbered, newValue, address);
     3175    }
     3176   
     3177    void atomicRelaxedWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address, RegisterID result)
     3178    {
     3179        atomicStrongCAS8(cond, expectedAndClobbered, newValue, address, result);
     3180    }
     3181
     3182    void atomicRelaxedWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address, RegisterID result)
     3183    {
     3184        atomicStrongCAS8(cond, expectedAndClobbered, newValue, address, result);
     3185    }
     3186
     3187    void atomicRelaxedWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address, RegisterID result)
     3188    {
     3189        atomicStrongCAS16(cond, expectedAndClobbered, newValue, address, result);
     3190    }
     3191
     3192    void atomicRelaxedWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address, RegisterID result)
     3193    {
     3194        atomicStrongCAS16(cond, expectedAndClobbered, newValue, address, result);
     3195    }
     3196
     3197    void atomicRelaxedWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address, RegisterID result)
     3198    {
     3199        atomicStrongCAS32(cond, expectedAndClobbered, newValue, address, result);
     3200    }
     3201
     3202    void atomicRelaxedWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address, RegisterID result)
     3203    {
     3204        atomicStrongCAS32(cond, expectedAndClobbered, newValue, address, result);
     3205    }
     3206
     3207    Jump branchAtomicRelaxedWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address)
     3208    {
     3209        return branchAtomicStrongCAS8(cond, expectedAndClobbered, newValue, address);
     3210    }
     3211
     3212    Jump branchAtomicRelaxedWeakCAS8(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address)
     3213    {
     3214        return branchAtomicStrongCAS8(cond, expectedAndClobbered, newValue, address);
     3215    }
     3216
     3217    Jump branchAtomicRelaxedWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address)
     3218    {
     3219        return branchAtomicStrongCAS16(cond, expectedAndClobbered, newValue, address);
     3220    }
     3221
     3222    Jump branchAtomicRelaxedWeakCAS16(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address)
     3223    {
     3224        return branchAtomicStrongCAS16(cond, expectedAndClobbered, newValue, address);
     3225    }
     3226
     3227    Jump branchAtomicRelaxedWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, Address address)
     3228    {
     3229        return branchAtomicStrongCAS32(cond, expectedAndClobbered, newValue, address);
     3230    }
     3231
     3232    Jump branchAtomicRelaxedWeakCAS32(StatusCondition cond, RegisterID expectedAndClobbered, RegisterID newValue, BaseIndex address)
     3233    {
     3234        return branchAtomicStrongCAS32(cond, expectedAndClobbered, newValue, address);
     3235    }
     3236   
     3237    void atomicAdd8(TrustedImm32 imm, Address address)
     3238    {
     3239        m_assembler.lock();
     3240        add8(imm, address);
     3241    }
     3242   
     3243    void atomicAdd8(TrustedImm32 imm, BaseIndex address)
     3244    {
     3245        m_assembler.lock();
     3246        add8(imm, address);
     3247    }
     3248   
     3249    void atomicAdd8(RegisterID reg, Address address)
     3250    {
     3251        m_assembler.lock();
     3252        add8(reg, address);
     3253    }
     3254   
     3255    void atomicAdd8(RegisterID reg, BaseIndex address)
     3256    {
     3257        m_assembler.lock();
     3258        add8(reg, address);
     3259    }
     3260   
     3261    void atomicAdd16(TrustedImm32 imm, Address address)
     3262    {
     3263        m_assembler.lock();
     3264        add16(imm, address);
     3265    }
     3266   
     3267    void atomicAdd16(TrustedImm32 imm, BaseIndex address)
     3268    {
     3269        m_assembler.lock();
     3270        add16(imm, address);
     3271    }
     3272   
     3273    void atomicAdd16(RegisterID reg, Address address)
     3274    {
     3275        m_assembler.lock();
     3276        add16(reg, address);
     3277    }
     3278   
     3279    void atomicAdd16(RegisterID reg, BaseIndex address)
     3280    {
     3281        m_assembler.lock();
     3282        add16(reg, address);
     3283    }
     3284   
     3285    void atomicAdd32(TrustedImm32 imm, Address address)
     3286    {
     3287        m_assembler.lock();
     3288        add32(imm, address);
     3289    }
     3290   
     3291    void atomicAdd32(TrustedImm32 imm, BaseIndex address)
     3292    {
     3293        m_assembler.lock();
     3294        add32(imm, address);
     3295    }
     3296   
     3297    void atomicAdd32(RegisterID reg, Address address)
     3298    {
     3299        m_assembler.lock();
     3300        add32(reg, address);
     3301    }
     3302   
     3303    void atomicAdd32(RegisterID reg, BaseIndex address)
     3304    {
     3305        m_assembler.lock();
     3306        add32(reg, address);
     3307    }
     3308   
     3309    void atomicSub8(TrustedImm32 imm, Address address)
     3310    {
     3311        m_assembler.lock();
     3312        sub8(imm, address);
     3313    }
     3314   
     3315    void atomicSub8(TrustedImm32 imm, BaseIndex address)
     3316    {
     3317        m_assembler.lock();
     3318        sub8(imm, address);
     3319    }
     3320   
     3321    void atomicSub8(RegisterID reg, Address address)
     3322    {
     3323        m_assembler.lock();
     3324        sub8(reg, address);
     3325    }
     3326   
     3327    void atomicSub8(RegisterID reg, BaseIndex address)
     3328    {
     3329        m_assembler.lock();
     3330        sub8(reg, address);
     3331    }
     3332   
     3333    void atomicSub16(TrustedImm32 imm, Address address)
     3334    {
     3335        m_assembler.lock();
     3336        sub16(imm, address);
     3337    }
     3338   
     3339    void atomicSub16(TrustedImm32 imm, BaseIndex address)
     3340    {
     3341        m_assembler.lock();
     3342        sub16(imm, address);
     3343    }
     3344   
     3345    void atomicSub16(RegisterID reg, Address address)
     3346    {
     3347        m_assembler.lock();
     3348        sub16(reg, address);
     3349    }
     3350   
     3351    void atomicSub16(RegisterID reg, BaseIndex address)
     3352    {
     3353        m_assembler.lock();
     3354        sub16(reg, address);
     3355    }
     3356   
     3357    void atomicSub32(TrustedImm32 imm, Address address)
     3358    {
     3359        m_assembler.lock();
     3360        sub32(imm, address);
     3361    }
     3362   
     3363    void atomicSub32(TrustedImm32 imm, BaseIndex address)
     3364    {
     3365        m_assembler.lock();
     3366        sub32(imm, address);
     3367    }
     3368   
     3369    void atomicSub32(RegisterID reg, Address address)
     3370    {
     3371        m_assembler.lock();
     3372        sub32(reg, address);
     3373    }
     3374   
     3375    void atomicSub32(RegisterID reg, BaseIndex address)
     3376    {
     3377        m_assembler.lock();
     3378        sub32(reg, address);
     3379    }
     3380   
     3381    void atomicAnd8(TrustedImm32 imm, Address address)
     3382    {
     3383        m_assembler.lock();
     3384        and8(imm, address);
     3385    }
     3386   
     3387    void atomicAnd8(TrustedImm32 imm, BaseIndex address)
     3388    {
     3389        m_assembler.lock();
     3390        and8(imm, address);
     3391    }
     3392   
     3393    void atomicAnd8(RegisterID reg, Address address)
     3394    {
     3395        m_assembler.lock();
     3396        and8(reg, address);
     3397    }
     3398   
     3399    void atomicAnd8(RegisterID reg, BaseIndex address)
     3400    {
     3401        m_assembler.lock();
     3402        and8(reg, address);
     3403    }
     3404   
     3405    void atomicAnd16(TrustedImm32 imm, Address address)
     3406    {
     3407        m_assembler.lock();
     3408        and16(imm, address);
     3409    }
     3410   
     3411    void atomicAnd16(TrustedImm32 imm, BaseIndex address)
     3412    {
     3413        m_assembler.lock();
     3414        and16(imm, address);
     3415    }
     3416   
     3417    void atomicAnd16(RegisterID reg, Address address)
     3418    {
     3419        m_assembler.lock();
     3420        and16(reg, address);
     3421    }
     3422   
     3423    void atomicAnd16(RegisterID reg, BaseIndex address)
     3424    {
     3425        m_assembler.lock();
     3426        and16(reg, address);
     3427    }
     3428   
     3429    void atomicAnd32(TrustedImm32 imm, Address address)
     3430    {
     3431        m_assembler.lock();
     3432        and32(imm, address);
     3433    }
     3434   
     3435    void atomicAnd32(TrustedImm32 imm, BaseIndex address)
     3436    {
     3437        m_assembler.lock();
     3438        and32(imm, address);
     3439    }
     3440   
     3441    void atomicAnd32(RegisterID reg, Address address)
     3442    {
     3443        m_assembler.lock();
     3444        and32(reg, address);
     3445    }
     3446   
     3447    void atomicAnd32(RegisterID reg, BaseIndex address)
     3448    {
     3449        m_assembler.lock();
     3450        and32(reg, address);
     3451    }
     3452   
     3453    void atomicOr8(TrustedImm32 imm, Address address)
     3454    {
     3455        m_assembler.lock();
     3456        or8(imm, address);
     3457    }
     3458   
     3459    void atomicOr8(TrustedImm32 imm, BaseIndex address)
     3460    {
     3461        m_assembler.lock();
     3462        or8(imm, address);
     3463    }
     3464   
     3465    void atomicOr8(RegisterID reg, Address address)
     3466    {
     3467        m_assembler.lock();
     3468        or8(reg, address);
     3469    }
     3470   
     3471    void atomicOr8(RegisterID reg, BaseIndex address)
     3472    {
     3473        m_assembler.lock();
     3474        or8(reg, address);
     3475    }
     3476   
     3477    void atomicOr16(TrustedImm32 imm, Address address)
     3478    {
     3479        m_assembler.lock();
     3480        or16(imm, address);
     3481    }
     3482   
     3483    void atomicOr16(TrustedImm32 imm, BaseIndex address)
     3484    {
     3485        m_assembler.lock();
     3486        or16(imm, address);
     3487    }
     3488   
     3489    void atomicOr16(RegisterID reg, Address address)
     3490    {
     3491        m_assembler.lock();
     3492        or16(reg, address);
     3493    }
     3494   
     3495    void atomicOr16(RegisterID reg, BaseIndex address)
     3496    {
     3497        m_assembler.lock();
     3498        or16(reg, address);
     3499    }
     3500   
     3501    void atomicOr32(TrustedImm32 imm, Address address)
     3502    {
     3503        m_assembler.lock();
     3504        or32(imm, address);
     3505    }
     3506   
     3507    void atomicOr32(TrustedImm32 imm, BaseIndex address)
     3508    {
     3509        m_assembler.lock();
     3510        or32(imm, address);
     3511    }
     3512   
     3513    void atomicOr32(RegisterID reg, Address address)
     3514    {
     3515        m_assembler.lock();
     3516        or32(reg, address);
     3517    }
     3518   
     3519    void atomicOr32(RegisterID reg, BaseIndex address)
     3520    {
     3521        m_assembler.lock();
     3522        or32(reg, address);
     3523    }
     3524   
     3525    void atomicXor8(TrustedImm32 imm, Address address)
     3526    {
     3527        m_assembler.lock();
     3528        xor8(imm, address);
     3529    }
     3530   
     3531    void atomicXor8(TrustedImm32 imm, BaseIndex address)
     3532    {
     3533        m_assembler.lock();
     3534        xor8(imm, address);
     3535    }
     3536   
     3537    void atomicXor8(RegisterID reg, Address address)
     3538    {
     3539        m_assembler.lock();
     3540        xor8(reg, address);
     3541    }
     3542   
     3543    void atomicXor8(RegisterID reg, BaseIndex address)
     3544    {
     3545        m_assembler.lock();
     3546        xor8(reg, address);
     3547    }
     3548   
     3549    void atomicXor16(TrustedImm32 imm, Address address)
     3550    {
     3551        m_assembler.lock();
     3552        xor16(imm, address);
     3553    }
     3554   
     3555    void atomicXor16(TrustedImm32 imm, BaseIndex address)
     3556    {
     3557        m_assembler.lock();
     3558        xor16(imm, address);
     3559    }
     3560   
     3561    void atomicXor16(RegisterID reg, Address address)
     3562    {
     3563        m_assembler.lock();
     3564        xor16(reg, address);
     3565    }
     3566   
     3567    void atomicXor16(RegisterID reg, BaseIndex address)
     3568    {
     3569        m_assembler.lock();
     3570        xor16(reg, address);
     3571    }
     3572   
     3573    void atomicXor32(TrustedImm32 imm, Address address)
     3574    {
     3575        m_assembler.lock();
     3576        xor32(imm, address);
     3577    }
     3578   
     3579    void atomicXor32(TrustedImm32 imm, BaseIndex address)
     3580    {
     3581        m_assembler.lock();
     3582        xor32(imm, address);
     3583    }
     3584   
     3585    void atomicXor32(RegisterID reg, Address address)
     3586    {
     3587        m_assembler.lock();
     3588        xor32(reg, address);
     3589    }
     3590   
     3591    void atomicXor32(RegisterID reg, BaseIndex address)
     3592    {
     3593        m_assembler.lock();
     3594        xor32(reg, address);
     3595    }
     3596   
     3597    void atomicNeg8(Address address)
     3598    {
     3599        m_assembler.lock();
     3600        neg8(address);
     3601    }
     3602   
     3603    void atomicNeg8(BaseIndex address)
     3604    {
     3605        m_assembler.lock();
     3606        neg8(address);
     3607    }
     3608   
     3609    void atomicNeg16(Address address)
     3610    {
     3611        m_assembler.lock();
     3612        neg16(address);
     3613    }
     3614   
     3615    void atomicNeg16(BaseIndex address)
     3616    {
     3617        m_assembler.lock();
     3618        neg16(address);
     3619    }
     3620   
     3621    void atomicNeg32(Address address)
     3622    {
     3623        m_assembler.lock();
     3624        neg32(address);
     3625    }
     3626   
     3627    void atomicNeg32(BaseIndex address)
     3628    {
     3629        m_assembler.lock();
     3630        neg32(address);
     3631    }
     3632   
     3633    void atomicNot8(Address address)
     3634    {
     3635        m_assembler.lock();
     3636        not8(address);
     3637    }
     3638   
     3639    void atomicNot8(BaseIndex address)
     3640    {
     3641        m_assembler.lock();
     3642        not8(address);
     3643    }
     3644   
     3645    void atomicNot16(Address address)
     3646    {
     3647        m_assembler.lock();
     3648        not16(address);
     3649    }
     3650   
     3651    void atomicNot16(BaseIndex address)
     3652    {
     3653        m_assembler.lock();
     3654        not16(address);
     3655    }
     3656   
     3657    void atomicNot32(Address address)
     3658    {
     3659        m_assembler.lock();
     3660        not32(address);
     3661    }
     3662   
     3663    void atomicNot32(BaseIndex address)
     3664    {
     3665        m_assembler.lock();
     3666        not32(address);
     3667    }
     3668   
     3669    void atomicXchgAdd8(RegisterID reg, Address address)
     3670    {
     3671        m_assembler.lock();
     3672        m_assembler.xaddb_rm(reg, address.offset, address.base);
     3673    }
     3674   
     3675    void atomicXchgAdd8(RegisterID reg, BaseIndex address)
     3676    {
     3677        m_assembler.lock();
     3678        m_assembler.xaddb_rm(reg, address.offset, address.base, address.index, address.scale);
     3679    }
     3680   
     3681    void atomicXchgAdd16(RegisterID reg, Address address)
     3682    {
     3683        m_assembler.lock();
     3684        m_assembler.xaddw_rm(reg, address.offset, address.base);
     3685    }
     3686   
     3687    void atomicXchgAdd16(RegisterID reg, BaseIndex address)
     3688    {
     3689        m_assembler.lock();
     3690        m_assembler.xaddw_rm(reg, address.offset, address.base, address.index, address.scale);
     3691    }
     3692   
     3693    void atomicXchgAdd32(RegisterID reg, Address address)
     3694    {
     3695        m_assembler.lock();
     3696        m_assembler.xaddl_rm(reg, address.offset, address.base);
     3697    }
     3698   
     3699    void atomicXchgAdd32(RegisterID reg, BaseIndex address)
     3700    {
     3701        m_assembler.lock();
     3702        m_assembler.xaddl_rm(reg, address.offset, address.base, address.index, address.scale);
     3703    }
     3704   
     3705    void atomicXchg8(RegisterID reg, Address address)
     3706    {
     3707        m_assembler.lock();
     3708        m_assembler.xchgb_rm(reg, address.offset, address.base);
     3709    }
     3710   
     3711    void atomicXchg8(RegisterID reg, BaseIndex address)
     3712    {
     3713        m_assembler.lock();
     3714        m_assembler.xchgb_rm(reg, address.offset, address.base, address.index, address.scale);
     3715    }
     3716   
     3717    void atomicXchg16(RegisterID reg, Address address)
     3718    {
     3719        m_assembler.lock();
     3720        m_assembler.xchgw_rm(reg, address.offset, address.base);
     3721    }
     3722   
     3723    void atomicXchg16(RegisterID reg, BaseIndex address)
     3724    {
     3725        m_assembler.lock();
     3726        m_assembler.xchgw_rm(reg, address.offset, address.base, address.index, address.scale);
     3727    }
     3728   
     3729    void atomicXchg32(RegisterID reg, Address address)
     3730    {
     3731        m_assembler.lock();
     3732        m_assembler.xchgl_rm(reg, address.offset, address.base);
     3733    }
     3734   
     3735    void atomicXchg32(RegisterID reg, BaseIndex address)
     3736    {
     3737        m_assembler.lock();
     3738        m_assembler.xchgl_rm(reg, address.offset, address.base, address.index, address.scale);
     3739    }
     3740   
     3741    void loadAcq8(Address src, RegisterID dest)
     3742    {
     3743        load8(src, dest);
     3744    }
     3745   
     3746    void loadAcq8(BaseIndex src, RegisterID dest)
     3747    {
     3748        load8(src, dest);
     3749    }
     3750   
     3751    void loadAcq8SignedExtendTo32(Address src, RegisterID dest)
     3752    {
     3753        load8SignedExtendTo32(src, dest);
     3754    }
     3755   
     3756    void loadAcq8SignedExtendTo32(BaseIndex src, RegisterID dest)
     3757    {
     3758        load8SignedExtendTo32(src, dest);
     3759    }
     3760   
     3761    void loadAcq16(Address src, RegisterID dest)
     3762    {
     3763        load16(src, dest);
     3764    }
     3765   
     3766    void loadAcq16(BaseIndex src, RegisterID dest)
     3767    {
     3768        load16(src, dest);
     3769    }
     3770   
     3771    void loadAcq16SignedExtendTo32(Address src, RegisterID dest)
     3772    {
     3773        load16SignedExtendTo32(src, dest);
     3774    }
     3775   
     3776    void loadAcq16SignedExtendTo32(BaseIndex src, RegisterID dest)
     3777    {
     3778        load16SignedExtendTo32(src, dest);
     3779    }
     3780   
     3781    void loadAcq32(Address src, RegisterID dest)
     3782    {
     3783        load32(src, dest);
     3784    }
     3785   
     3786    void loadAcq32(BaseIndex src, RegisterID dest)
     3787    {
     3788        load32(src, dest);
     3789    }
     3790   
     3791    void storeRel8(RegisterID src, Address dest)
     3792    {
     3793        store8(src, dest);
     3794    }
     3795   
     3796    void storeRel8(RegisterID src, BaseIndex dest)
     3797    {
     3798        store8(src, dest);
     3799    }
     3800   
     3801    void storeRel8(TrustedImm32 imm, Address dest)
     3802    {
     3803        store8(imm, dest);
     3804    }
     3805   
     3806    void storeRel8(TrustedImm32 imm, BaseIndex dest)
     3807    {
     3808        store8(imm, dest);
     3809    }
     3810   
     3811    void storeRel16(RegisterID src, Address dest)
     3812    {
     3813        store16(src, dest);
     3814    }
     3815   
     3816    void storeRel16(RegisterID src, BaseIndex dest)
     3817    {
     3818        store16(src, dest);
     3819    }
     3820   
     3821    void storeRel16(TrustedImm32 imm, Address dest)
     3822    {
     3823        store16(imm, dest);
     3824    }
     3825   
     3826    void storeRel16(TrustedImm32 imm, BaseIndex dest)
     3827    {
     3828        store16(imm, dest);
     3829    }
     3830   
     3831    void storeRel32(RegisterID src, Address dest)
     3832    {
     3833        store32(src, dest);
     3834    }
     3835   
     3836    void storeRel32(RegisterID src, BaseIndex dest)
     3837    {
     3838        store32(src, dest);
     3839    }
     3840   
     3841    void storeRel32(TrustedImm32 imm, Address dest)
     3842    {
     3843        store32(imm, dest);
     3844    }
     3845   
     3846    void storeRel32(TrustedImm32 imm, BaseIndex dest)
     3847    {
     3848        store32(imm, dest);
     3849    }
     3850   
    27493851    // We take this to mean that it prevents motion of normal stores. So, it's a no-op on x86.
    27503852    void storeFence()
    … …  
    28393941    }
    28403942
     3943    X86Assembler::Condition x86Condition(StatusCondition cond)
     3944    {
     3945        switch (cond) {
     3946        case Success:
     3947            return X86Assembler::ConditionE;
     3948        case Failure:
     3949            return X86Assembler::ConditionNE;
     3950        }
     3951        RELEASE_ASSERT_NOT_REACHED();
     3952        return X86Assembler::ConditionE;
     3953    }
     3954
    28413955    void set32(X86Assembler::Condition cond, RegisterID dest)
    28423956    {
    … …  
    29334047        srcIsNonZero.link(this);
    29344048    }
     4049   
     4050    template<typename Func>
     4051    void atomicStrongCAS(StatusCondition cond, RegisterID expectedAndResult, RegisterID result, const Func& func)
     4052    {
     4053        swap(expectedAndResult, X86Registers::eax);
     4054        m_assembler.lock();
     4055        func();
     4056        swap(expectedAndResult, X86Registers::eax);
     4057        set32(x86Condition(cond), result);
     4058    }
     4059
     4060    template<typename Func>
     4061    void atomicStrongCAS(RegisterID expectedAndResult, const Func& func)
     4062    {
     4063        swap(expectedAndResult, X86Registers::eax);
     4064        m_assembler.lock();
     4065        func();
     4066        swap(expectedAndResult, X86Registers::eax);
     4067    }
     4068
     4069    template<typename Func>
     4070    Jump branchAtomicStrongCAS(StatusCondition cond, RegisterID expectedAndResult, const Func& func)
     4071    {
     4072        swap(expectedAndResult, X86Registers::eax);
     4073        m_assembler.lock();
     4074        func();
     4075        swap(expectedAndResult, X86Registers::eax);
     4076        return Jump(m_assembler.jCC(x86Condition(cond)));
     4077    }
    29354078
    29364079private:
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