Changeset 219740 in webkit for trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h

Timestamp:

Jul 21, 2017, 1:44:33 PM (8 years ago)

Author:

[email protected]

Message:

Refactor MASM probe CPUState to use arrays for register storage.
​https://bugs.webkit.org/show_bug.cgi?id=174694

Reviewed by Keith Miller.

Using arrays for register storage in CPUState allows us to do away with the
huge switch statements to decode each register id. We can now simply index into
the arrays.

With this patch, we now:

1. Remove the need for macros for defining the list of CPU registers. We can go back to simple enums. This makes the code easier to read.

2. Make the assembler the authority on register names. Most of this code is moved into the assembler from GPRInfo and FPRInfo. GPRInfo and FPRInfo now forwards to the assembler.

3. Make the assembler the authority on the number of registers of each type.

4. Fix a "bug" in ARMv7's lastRegister(). It was previously omitting lr and pc. This is inconsistent with how every other CPU architecture implements lastRegister(). This patch fixes it to return the true last GPR i.e. pc, but updates RegisterSet::reservedHardwareRegisters() to exclude those registers.

• assembler/ARM64Assembler.h:

(JSC::ARM64Assembler::numberOfRegisters):
(JSC::ARM64Assembler::firstSPRegister):
(JSC::ARM64Assembler::lastSPRegister):
(JSC::ARM64Assembler::numberOfSPRegisters):
(JSC::ARM64Assembler::numberOfFPRegisters):
(JSC::ARM64Assembler::gprName):
(JSC::ARM64Assembler::sprName):
(JSC::ARM64Assembler::fprName):

• assembler/ARMAssembler.h:

(JSC::ARMAssembler::numberOfRegisters):
(JSC::ARMAssembler::firstSPRegister):
(JSC::ARMAssembler::lastSPRegister):
(JSC::ARMAssembler::numberOfSPRegisters):
(JSC::ARMAssembler::numberOfFPRegisters):
(JSC::ARMAssembler::gprName):
(JSC::ARMAssembler::sprName):
(JSC::ARMAssembler::fprName):

• assembler/ARMv7Assembler.h:

(JSC::ARMv7Assembler::lastRegister):
(JSC::ARMv7Assembler::numberOfRegisters):
(JSC::ARMv7Assembler::firstSPRegister):
(JSC::ARMv7Assembler::lastSPRegister):
(JSC::ARMv7Assembler::numberOfSPRegisters):
(JSC::ARMv7Assembler::numberOfFPRegisters):
(JSC::ARMv7Assembler::gprName):
(JSC::ARMv7Assembler::sprName):
(JSC::ARMv7Assembler::fprName):

• assembler/AbstractMacroAssembler.h:

(JSC::AbstractMacroAssembler::numberOfRegisters):
(JSC::AbstractMacroAssembler::gprName):
(JSC::AbstractMacroAssembler::firstSPRegister):
(JSC::AbstractMacroAssembler::lastSPRegister):
(JSC::AbstractMacroAssembler::numberOfSPRegisters):
(JSC::AbstractMacroAssembler::sprName):
(JSC::AbstractMacroAssembler::numberOfFPRegisters):
(JSC::AbstractMacroAssembler::fprName):

• assembler/MIPSAssembler.h:

(JSC::MIPSAssembler::numberOfRegisters):
(JSC::MIPSAssembler::firstSPRegister):
(JSC::MIPSAssembler::lastSPRegister):
(JSC::MIPSAssembler::numberOfSPRegisters):
(JSC::MIPSAssembler::numberOfFPRegisters):
(JSC::MIPSAssembler::gprName):
(JSC::MIPSAssembler::sprName):
(JSC::MIPSAssembler::fprName):

• assembler/MacroAssembler.h:

(JSC::MacroAssembler::CPUState::gprName):
(JSC::MacroAssembler::CPUState::sprName):
(JSC::MacroAssembler::CPUState::fprName):
(JSC::MacroAssembler::CPUState::gpr):
(JSC::MacroAssembler::CPUState::spr):
(JSC::MacroAssembler::CPUState::fpr):
(JSC::MacroAssembler::CPUState::pc):
(JSC::MacroAssembler::CPUState::fp):
(JSC::MacroAssembler::CPUState::sp):
(JSC::ProbeContext::gpr):
(JSC::ProbeContext::spr):
(JSC::ProbeContext::fpr):
(JSC::ProbeContext::gprName):
(JSC::ProbeContext::sprName):
(JSC::ProbeContext::fprName):
(JSC::MacroAssembler::numberOfRegisters): Deleted.
(JSC::MacroAssembler::numberOfFPRegisters): Deleted.

• assembler/MacroAssemblerARM.cpp:
• assembler/MacroAssemblerARM64.cpp:

(JSC::arm64ProbeTrampoline):

• assembler/MacroAssemblerARMv7.cpp:
• assembler/MacroAssemblerPrinter.cpp:

(JSC::Printer::nextID):
(JSC::Printer::printAllRegisters):
(JSC::Printer::printPCRegister):
(JSC::Printer::printRegisterID):
(JSC::Printer::printAddress):

• assembler/MacroAssemblerX86Common.cpp:
• assembler/X86Assembler.h:

(JSC::X86Assembler::numberOfRegisters):
(JSC::X86Assembler::firstSPRegister):
(JSC::X86Assembler::lastSPRegister):
(JSC::X86Assembler::numberOfSPRegisters):
(JSC::X86Assembler::numberOfFPRegisters):
(JSC::X86Assembler::gprName):
(JSC::X86Assembler::sprName):
(JSC::X86Assembler::fprName):

• jit/FPRInfo.h:

(JSC::FPRInfo::debugName):

• jit/GPRInfo.h:

(JSC::GPRInfo::debugName):

• jit/RegisterSet.cpp:

(JSC::RegisterSet::reservedHardwareRegisters):

File:

• trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h (modified) (3 diffs)

trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h

@@ -158 +158 @@
 namespace ARM64Registers {
 
-#define FOR_EACH_CPU_REGISTER(V) \
-    FOR_EACH_CPU_GPREGISTER(V) \
-    FOR_EACH_CPU_SPECIAL_REGISTER(V) \
-    FOR_EACH_CPU_FPREGISTER(V)
-
-// The following are defined as pairs of the following value:
-// 1. type of the storage needed to save the register value by the JIT probe.
-// 2. name of the register.
-#define FOR_EACH_CPU_GPREGISTER(V) \
-    /* Parameter/result registers */ \
-    V(void*, x0) \
-    V(void*, x1) \
-    V(void*, x2) \
-    V(void*, x3) \
-    V(void*, x4) \
-    V(void*, x5) \
-    V(void*, x6) \
-    V(void*, x7) \
-    /* Indirect result location register */ \
-    V(void*, x8) \
-    /* Temporary registers */ \
-    V(void*, x9) \
-    V(void*, x10) \
-    V(void*, x11) \
-    V(void*, x12) \
-    V(void*, x13) \
-    V(void*, x14) \
-    V(void*, x15) \
-    /* Intra-procedure-call scratch registers (temporary) */ \
-    V(void*, x16) \
-    V(void*, x17) \
-    /* Platform Register (temporary) */ \
-    V(void*, x18) \
-    /* Callee-saved */ \
-    V(void*, x19) \
-    V(void*, x20) \
-    V(void*, x21) \
-    V(void*, x22) \
-    V(void*, x23) \
-    V(void*, x24) \
-    V(void*, x25) \
-    V(void*, x26) \
-    V(void*, x27) \
-    V(void*, x28) \
-    /* Special */ \
-    V(void*, fp) \
-    V(void*, lr) \
-    V(void*, sp)
-
-#define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
-    V(void*, pc) \
-    V(void*, nzcv) \
-    V(void*, fpsr) \
-
-// ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
-// and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
-// However, we only use them for 64-bit doubles.
-#define FOR_EACH_CPU_FPREGISTER(V) \
-    /* Parameter/result registers */ \
-    V(double, q0) \
-    V(double, q1) \
-    V(double, q2) \
-    V(double, q3) \
-    V(double, q4) \
-    V(double, q5) \
-    V(double, q6) \
-    V(double, q7) \
-    /* Callee-saved (up to 64-bits only!) */ \
-    V(double, q8) \
-    V(double, q9) \
-    V(double, q10) \
-    V(double, q11) \
-    V(double, q12) \
-    V(double, q13) \
-    V(double, q14) \
-    V(double, q15) \
-    /* Temporary registers */ \
-    V(double, q16) \
-    V(double, q17) \
-    V(double, q18) \
-    V(double, q19) \
-    V(double, q20) \
-    V(double, q21) \
-    V(double, q22) \
-    V(double, q23) \
-    V(double, q24) \
-    V(double, q25) \
-    V(double, q26) \
-    V(double, q27) \
-    V(double, q28) \
-    V(double, q29) \
-    V(double, q30) \
-    V(double, q31)
-
 typedef enum {
-    #define DECLARE_REGISTER(_type, _regName) _regName,
-    FOR_EACH_CPU_GPREGISTER(DECLARE_REGISTER)
-    #undef DECLARE_REGISTER
+    // Parameter/result registers.
+    x0,
+    x1,
+    x2,
+    x3,
+    x4,
+    x5,
+    x6,
+    x7,
+    // Indirect result location register.
+    x8,
+    // Temporary registers.
+    x9,
+    x10,
+    x11,
+    x12,
+    x13,
+    x14,
+    x15,
+    // Intra-procedure-call scratch registers (temporary).
+    x16,
+    x17,
+    // Platform Register (temporary).
+    x18,
+    // Callee-saved.
+    x19,
+    x20,
+    x21,
+    x22,
+    x23,
+    x24,
+    x25,
+    x26,
+    x27,
+    x28,
+    // Special.
+    fp,
+    lr,
+    sp,
 
     ip0 = x16,
@@ -265 +207 @@
 
 typedef enum {
-    #define DECLARE_REGISTER(_type, _regName) _regName,
-    FOR_EACH_CPU_FPREGISTER(DECLARE_REGISTER)
-    #undef DECLARE_REGISTER
+    pc,
+    nzcv,
+    fpsr
+} SPRegisterID;
+
+// ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
+// and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
+// However, we only use them for 64-bit doubles.
+typedef enum {
+    // Parameter/result registers.
+    q0,
+    q1,
+    q2,
+    q3,
+    q4,
+    q5,
+    q6,
+    q7,
+    // Callee-saved (up to 64-bits only!).
+    q8,
+    q9,
+    q10,
+    q11,
+    q12,
+    q13,
+    q14,
+    q15,
+    // Temporary registers.
+    q16,
+    q17,
+    q18,
+    q19,
+    q20,
+    q21,
+    q22,
+    q23,
+    q24,
+    q25,
+    q26,
+    q27,
+    q28,
+    q29,
+    q30,
+    q31,
 } FPRegisterID;
 
@@ -278 +261 @@
 public:
     typedef ARM64Registers::RegisterID RegisterID;
+    typedef ARM64Registers::SPRegisterID SPRegisterID;
     typedef ARM64Registers::FPRegisterID FPRegisterID;
     
     static constexpr RegisterID firstRegister() { return ARM64Registers::x0; }
     static constexpr RegisterID lastRegister() { return ARM64Registers::sp; }
-    
+    static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
+
+    static constexpr SPRegisterID firstSPRegister() { return ARM64Registers::pc; }
+    static constexpr SPRegisterID lastSPRegister() { return ARM64Registers::fpsr; }
+    static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
+
     static constexpr FPRegisterID firstFPRegister() { return ARM64Registers::q0; }
     static constexpr FPRegisterID lastFPRegister() { return ARM64Registers::q31; }
+    static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }
+
+    static const char* gprName(RegisterID id)
+    {
+        ASSERT(id >= firstRegister() && id <= lastRegister());
+        static const char* const nameForRegister[numberOfRegisters()] = {
+            "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+            "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
+            "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
+            "r24", "r25", "r26", "r27", "r28", "fp", "lr", "sp"
+        };
+        return nameForRegister[id];
+    }
+
+    static const char* sprName(SPRegisterID id)
+    {
+        ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
+        static const char* const nameForRegister[numberOfSPRegisters()] = {
+            "pc", "nzcv", "fpsr"
+        };
+        return nameForRegister[id];
+    }
+
+    static const char* fprName(FPRegisterID id)
+    {
+        ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
+        static const char* const nameForRegister[numberOfFPRegisters()] = {
+            "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
+            "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
+            "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
+            "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
+        };
+        return nameForRegister[id];
+    }
 
 private: