Changeset 219740 in webkit for trunk/Source/JavaScriptCore/assembler/MIPSAssembler.h

Timestamp:

Jul 21, 2017, 1:44:33 PM (8 years ago)

Author:

[email protected]

Message:

Refactor MASM probe CPUState to use arrays for register storage.
​https://bugs.webkit.org/show_bug.cgi?id=174694

Reviewed by Keith Miller.

Using arrays for register storage in CPUState allows us to do away with the
huge switch statements to decode each register id. We can now simply index into
the arrays.

With this patch, we now:

1. Remove the need for macros for defining the list of CPU registers. We can go back to simple enums. This makes the code easier to read.

2. Make the assembler the authority on register names. Most of this code is moved into the assembler from GPRInfo and FPRInfo. GPRInfo and FPRInfo now forwards to the assembler.

3. Make the assembler the authority on the number of registers of each type.

4. Fix a "bug" in ARMv7's lastRegister(). It was previously omitting lr and pc. This is inconsistent with how every other CPU architecture implements lastRegister(). This patch fixes it to return the true last GPR i.e. pc, but updates RegisterSet::reservedHardwareRegisters() to exclude those registers.

• assembler/ARM64Assembler.h:

(JSC::ARM64Assembler::numberOfRegisters):
(JSC::ARM64Assembler::firstSPRegister):
(JSC::ARM64Assembler::lastSPRegister):
(JSC::ARM64Assembler::numberOfSPRegisters):
(JSC::ARM64Assembler::numberOfFPRegisters):
(JSC::ARM64Assembler::gprName):
(JSC::ARM64Assembler::sprName):
(JSC::ARM64Assembler::fprName):

• assembler/ARMAssembler.h:

(JSC::ARMAssembler::numberOfRegisters):
(JSC::ARMAssembler::firstSPRegister):
(JSC::ARMAssembler::lastSPRegister):
(JSC::ARMAssembler::numberOfSPRegisters):
(JSC::ARMAssembler::numberOfFPRegisters):
(JSC::ARMAssembler::gprName):
(JSC::ARMAssembler::sprName):
(JSC::ARMAssembler::fprName):

• assembler/ARMv7Assembler.h:

(JSC::ARMv7Assembler::lastRegister):
(JSC::ARMv7Assembler::numberOfRegisters):
(JSC::ARMv7Assembler::firstSPRegister):
(JSC::ARMv7Assembler::lastSPRegister):
(JSC::ARMv7Assembler::numberOfSPRegisters):
(JSC::ARMv7Assembler::numberOfFPRegisters):
(JSC::ARMv7Assembler::gprName):
(JSC::ARMv7Assembler::sprName):
(JSC::ARMv7Assembler::fprName):

• assembler/AbstractMacroAssembler.h:

(JSC::AbstractMacroAssembler::numberOfRegisters):
(JSC::AbstractMacroAssembler::gprName):
(JSC::AbstractMacroAssembler::firstSPRegister):
(JSC::AbstractMacroAssembler::lastSPRegister):
(JSC::AbstractMacroAssembler::numberOfSPRegisters):
(JSC::AbstractMacroAssembler::sprName):
(JSC::AbstractMacroAssembler::numberOfFPRegisters):
(JSC::AbstractMacroAssembler::fprName):

• assembler/MIPSAssembler.h:

(JSC::MIPSAssembler::numberOfRegisters):
(JSC::MIPSAssembler::firstSPRegister):
(JSC::MIPSAssembler::lastSPRegister):
(JSC::MIPSAssembler::numberOfSPRegisters):
(JSC::MIPSAssembler::numberOfFPRegisters):
(JSC::MIPSAssembler::gprName):
(JSC::MIPSAssembler::sprName):
(JSC::MIPSAssembler::fprName):

• assembler/MacroAssembler.h:

(JSC::MacroAssembler::CPUState::gprName):
(JSC::MacroAssembler::CPUState::sprName):
(JSC::MacroAssembler::CPUState::fprName):
(JSC::MacroAssembler::CPUState::gpr):
(JSC::MacroAssembler::CPUState::spr):
(JSC::MacroAssembler::CPUState::fpr):
(JSC::MacroAssembler::CPUState::pc):
(JSC::MacroAssembler::CPUState::fp):
(JSC::MacroAssembler::CPUState::sp):
(JSC::ProbeContext::gpr):
(JSC::ProbeContext::spr):
(JSC::ProbeContext::fpr):
(JSC::ProbeContext::gprName):
(JSC::ProbeContext::sprName):
(JSC::ProbeContext::fprName):
(JSC::MacroAssembler::numberOfRegisters): Deleted.
(JSC::MacroAssembler::numberOfFPRegisters): Deleted.

• assembler/MacroAssemblerARM.cpp:
• assembler/MacroAssemblerARM64.cpp:

(JSC::arm64ProbeTrampoline):

• assembler/MacroAssemblerARMv7.cpp:
• assembler/MacroAssemblerPrinter.cpp:

(JSC::Printer::nextID):
(JSC::Printer::printAllRegisters):
(JSC::Printer::printPCRegister):
(JSC::Printer::printRegisterID):
(JSC::Printer::printAddress):

• assembler/MacroAssemblerX86Common.cpp:
• assembler/X86Assembler.h:

(JSC::X86Assembler::numberOfRegisters):
(JSC::X86Assembler::firstSPRegister):
(JSC::X86Assembler::lastSPRegister):
(JSC::X86Assembler::numberOfSPRegisters):
(JSC::X86Assembler::numberOfFPRegisters):
(JSC::X86Assembler::gprName):
(JSC::X86Assembler::sprName):
(JSC::X86Assembler::fprName):

• jit/FPRInfo.h:

(JSC::FPRInfo::debugName):

• jit/GPRInfo.h:

(JSC::GPRInfo::debugName):

• jit/RegisterSet.cpp:

(JSC::RegisterSet::reservedHardwareRegisters):

File:

• trunk/Source/JavaScriptCore/assembler/MIPSAssembler.h (modified) (3 diffs)

trunk/Source/JavaScriptCore/assembler/MIPSAssembler.h

@@ -109 +109 @@
 } RegisterID;
 
+// Currently, we don't have support for any special purpose registers.
+typedef enum {
+    firstInvalidSPR,
+    lastInvalidSPR = -1,
+} SPRegisterID;
+
 typedef enum {
     f0,
@@ -149 +155 @@
 public:
     typedef MIPSRegisters::RegisterID RegisterID;
+    typedef MIPSRegisters::SPRegisterID SPRegisterID;
     typedef MIPSRegisters::FPRegisterID FPRegisterID;
     typedef SegmentedVector<AssemblerLabel, 64> Jumps;
@@ -154 +161 @@
     static constexpr RegisterID firstRegister() { return MIPSRegisters::r0; }
     static constexpr RegisterID lastRegister() { return MIPSRegisters::r31; }
+    static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
+
+    static constexpr SPRegisterID firstSPRegister() { return MIPSRegisters::firstInvalidSPR; }
+    static constexpr SPRegisterID lastSPRegister() { return MIPSRegisters::lastInvalidSPR; }
+    static constexpr unsigned numberOfSPRegisters() { return 0; }
 
     static constexpr FPRegisterID firstFPRegister() { return MIPSRegisters::f0; }
     static constexpr FPRegisterID lastFPRegister() { return MIPSRegisters::f31; }
+    static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }
+    
+    static const char* gprName(RegisterID id)
+    {
+        ASSERT(id >= firstRegister() && id <= lastRegister());
+        static const char* const nameForRegister[numberOfRegisters()] = {
+            "zero", "at", "v0", "v1",
+            "a0", "a1", "a2", "a3",
+            "t0", "t1", "t2", "t3",
+            "t4", "t5", "t6", "t7"
+        };
+        return nameForRegister[id];
+    }
+
+    static const char* sprName(SPRegisterID id)
+    {
+        // Currently, we don't have support for any special purpose registers.
+        RELEASE_ASSERT_NOT_REACHED();
+    }
+
+    static const char* fprName(FPRegisterID id)
+    {
+        ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
+        static const char* const nameForRegister[numberOfFPRegisters()] = {
+            "f0", "f1", "f2", "f3",
+            "f4", "f5", "f6", "f7",
+            "f8", "f9", "f10", "f11",
+            "f12", "f13", "f14", "f15"
+            "f16", "f17", "f18", "f19"
+            "f20", "f21", "f22", "f23"
+            "f24", "f25", "f26", "f27"
+            "f28", "f29", "f30", "f31"
+        };
+        return nameForRegister[id];
+    }
 
     MIPSAssembler()