Ignore:
Timestamp:
Jul 21, 2017, 1:44:33 PM (8 years ago)
Author:
[email protected]
Message:

Refactor MASM probe CPUState to use arrays for register storage.
https://bugs.webkit.org/show_bug.cgi?id=174694

Reviewed by Keith Miller.

Using arrays for register storage in CPUState allows us to do away with the
huge switch statements to decode each register id. We can now simply index into
the arrays.

With this patch, we now:

  1. Remove the need for macros for defining the list of CPU registers. We can go back to simple enums. This makes the code easier to read.
  1. Make the assembler the authority on register names. Most of this code is moved into the assembler from GPRInfo and FPRInfo. GPRInfo and FPRInfo now forwards to the assembler.
  1. Make the assembler the authority on the number of registers of each type.
  1. Fix a "bug" in ARMv7's lastRegister(). It was previously omitting lr and pc. This is inconsistent with how every other CPU architecture implements lastRegister(). This patch fixes it to return the true last GPR i.e. pc, but updates RegisterSet::reservedHardwareRegisters() to exclude those registers.
  • assembler/ARM64Assembler.h:

(JSC::ARM64Assembler::numberOfRegisters):
(JSC::ARM64Assembler::firstSPRegister):
(JSC::ARM64Assembler::lastSPRegister):
(JSC::ARM64Assembler::numberOfSPRegisters):
(JSC::ARM64Assembler::numberOfFPRegisters):
(JSC::ARM64Assembler::gprName):
(JSC::ARM64Assembler::sprName):
(JSC::ARM64Assembler::fprName):

  • assembler/ARMAssembler.h:

(JSC::ARMAssembler::numberOfRegisters):
(JSC::ARMAssembler::firstSPRegister):
(JSC::ARMAssembler::lastSPRegister):
(JSC::ARMAssembler::numberOfSPRegisters):
(JSC::ARMAssembler::numberOfFPRegisters):
(JSC::ARMAssembler::gprName):
(JSC::ARMAssembler::sprName):
(JSC::ARMAssembler::fprName):

  • assembler/ARMv7Assembler.h:

(JSC::ARMv7Assembler::lastRegister):
(JSC::ARMv7Assembler::numberOfRegisters):
(JSC::ARMv7Assembler::firstSPRegister):
(JSC::ARMv7Assembler::lastSPRegister):
(JSC::ARMv7Assembler::numberOfSPRegisters):
(JSC::ARMv7Assembler::numberOfFPRegisters):
(JSC::ARMv7Assembler::gprName):
(JSC::ARMv7Assembler::sprName):
(JSC::ARMv7Assembler::fprName):

  • assembler/AbstractMacroAssembler.h:

(JSC::AbstractMacroAssembler::numberOfRegisters):
(JSC::AbstractMacroAssembler::gprName):
(JSC::AbstractMacroAssembler::firstSPRegister):
(JSC::AbstractMacroAssembler::lastSPRegister):
(JSC::AbstractMacroAssembler::numberOfSPRegisters):
(JSC::AbstractMacroAssembler::sprName):
(JSC::AbstractMacroAssembler::numberOfFPRegisters):
(JSC::AbstractMacroAssembler::fprName):

  • assembler/MIPSAssembler.h:

(JSC::MIPSAssembler::numberOfRegisters):
(JSC::MIPSAssembler::firstSPRegister):
(JSC::MIPSAssembler::lastSPRegister):
(JSC::MIPSAssembler::numberOfSPRegisters):
(JSC::MIPSAssembler::numberOfFPRegisters):
(JSC::MIPSAssembler::gprName):
(JSC::MIPSAssembler::sprName):
(JSC::MIPSAssembler::fprName):

  • assembler/MacroAssembler.h:

(JSC::MacroAssembler::CPUState::gprName):
(JSC::MacroAssembler::CPUState::sprName):
(JSC::MacroAssembler::CPUState::fprName):
(JSC::MacroAssembler::CPUState::gpr):
(JSC::MacroAssembler::CPUState::spr):
(JSC::MacroAssembler::CPUState::fpr):
(JSC::MacroAssembler::CPUState::pc):
(JSC::MacroAssembler::CPUState::fp):
(JSC::MacroAssembler::CPUState::sp):
(JSC::ProbeContext::gpr):
(JSC::ProbeContext::spr):
(JSC::ProbeContext::fpr):
(JSC::ProbeContext::gprName):
(JSC::ProbeContext::sprName):
(JSC::ProbeContext::fprName):
(JSC::MacroAssembler::numberOfRegisters): Deleted.
(JSC::MacroAssembler::numberOfFPRegisters): Deleted.

  • assembler/MacroAssemblerARM.cpp:
  • assembler/MacroAssemblerARM64.cpp:

(JSC::arm64ProbeTrampoline):

  • assembler/MacroAssemblerARMv7.cpp:
  • assembler/MacroAssemblerPrinter.cpp:

(JSC::Printer::nextID):
(JSC::Printer::printAllRegisters):
(JSC::Printer::printPCRegister):
(JSC::Printer::printRegisterID):
(JSC::Printer::printAddress):

  • assembler/MacroAssemblerX86Common.cpp:
  • assembler/X86Assembler.h:

(JSC::X86Assembler::numberOfRegisters):
(JSC::X86Assembler::firstSPRegister):
(JSC::X86Assembler::lastSPRegister):
(JSC::X86Assembler::numberOfSPRegisters):
(JSC::X86Assembler::numberOfFPRegisters):
(JSC::X86Assembler::gprName):
(JSC::X86Assembler::sprName):
(JSC::X86Assembler::fprName):

  • jit/FPRInfo.h:

(JSC::FPRInfo::debugName):

  • jit/GPRInfo.h:

(JSC::GPRInfo::debugName):

  • jit/RegisterSet.cpp:

(JSC::RegisterSet::reservedHardwareRegisters):

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/Source/JavaScriptCore/assembler/X86Assembler.h

    r218782 r219740  
    4242namespace X86Registers {
    4343
    44 #define FOR_EACH_CPU_REGISTER(V) \
    45     FOR_EACH_CPU_GPREGISTER(V) \
    46     FOR_EACH_CPU_SPECIAL_REGISTER(V) \
    47     FOR_EACH_CPU_FPREGISTER(V)
    48 
    49 // The following are defined as pairs of the following value:
    50 // 1. type of the storage needed to save the register value by the JIT probe.
    51 // 2. name of the register.
    52 #define FOR_EACH_CPU_GPREGISTER(V) \
    53     V(void*, eax) \
    54     V(void*, ecx) \
    55     V(void*, edx) \
    56     V(void*, ebx) \
    57     V(void*, esp) \
    58     V(void*, ebp) \
    59     V(void*, esi) \
    60     V(void*, edi) \
    61     FOR_EACH_X86_64_CPU_GPREGISTER(V)
    62 
    63 #define FOR_EACH_CPU_SPECIAL_REGISTER(V) \
    64     V(void*, eip) \
    65     V(void*, eflags) \
    66 
    67 // Note: the JITs only stores double values in the FP registers.
    68 #define FOR_EACH_CPU_FPREGISTER(V) \
    69     V(double, xmm0) \
    70     V(double, xmm1) \
    71     V(double, xmm2) \
    72     V(double, xmm3) \
    73     V(double, xmm4) \
    74     V(double, xmm5) \
    75     V(double, xmm6) \
    76     V(double, xmm7) \
    77     FOR_EACH_X86_64_CPU_FPREGISTER(V)
    78 
    79 #if CPU(X86)
    80 
    81 #define FOR_EACH_X86_64_CPU_GPREGISTER(V) // Nothing to add.
    82 #define FOR_EACH_X86_64_CPU_FPREGISTER(V) // Nothing to add.
    83 
    84 #elif CPU(X86_64)
    85 
    86 #define FOR_EACH_X86_64_CPU_GPREGISTER(V) \
    87     V(void*, r8) \
    88     V(void*, r9) \
    89     V(void*, r10) \
    90     V(void*, r11) \
    91     V(void*, r12) \
    92     V(void*, r13) \
    93     V(void*, r14) \
    94     V(void*, r15)
    95 
    96 #define FOR_EACH_X86_64_CPU_FPREGISTER(V) \
    97     V(double, xmm8) \
    98     V(double, xmm9) \
    99     V(double, xmm10) \
    100     V(double, xmm11) \
    101     V(double, xmm12) \
    102     V(double, xmm13) \
    103     V(double, xmm14) \
    104     V(double, xmm15)
    105 
    106 #endif // CPU(X86_64)
    107 
    10844typedef enum {
    109     #define DECLARE_REGISTER(_type, _regName) _regName,
    110     FOR_EACH_CPU_GPREGISTER(DECLARE_REGISTER)
    111     #undef DECLARE_REGISTER
     45    eax,
     46    ecx,
     47    edx,
     48    ebx,
     49    esp,
     50    ebp,
     51    esi,
     52    edi,
     53#if CPU(X86_64)
     54    r8,
     55    r9,
     56    r10,
     57    r11,
     58    r12,
     59    r13,
     60    r14,
     61    r15
     62#endif
    11263} RegisterID;
    11364
    11465typedef enum {
    115     #define DECLARE_REGISTER(_type, _regName) _regName,
    116     FOR_EACH_CPU_FPREGISTER(DECLARE_REGISTER)
    117     #undef DECLARE_REGISTER
     66    eip,
     67    eflags
     68} SPRegisterID;
     69
     70typedef enum {
     71    xmm0,
     72    xmm1,
     73    xmm2,
     74    xmm3,
     75    xmm4,
     76    xmm5,
     77    xmm6,
     78    xmm7,
     79#if CPU(X86_64)
     80    xmm8,
     81    xmm9,
     82    xmm10,
     83    xmm11,
     84    xmm12,
     85    xmm13,
     86    xmm14,
     87    xmm15
     88#endif
    11889} XMMRegisterID;
    11990
     
    133104#endif
    134105    }
     106    static constexpr unsigned numberOfRegisters() { return lastRegister() - firstRegister() + 1; }
     107   
     108    typedef X86Registers::SPRegisterID SPRegisterID;
     109
     110    static constexpr SPRegisterID firstSPRegister() { return X86Registers::eip; }
     111    static constexpr SPRegisterID lastSPRegister() { return X86Registers::eflags; }
     112    static constexpr unsigned numberOfSPRegisters() { return lastSPRegister() - firstSPRegister() + 1; }
    135113   
    136114    typedef X86Registers::XMMRegisterID XMMRegisterID;
     
    146124#endif
    147125    }
    148 
     126    static constexpr unsigned numberOfFPRegisters() { return lastFPRegister() - firstFPRegister() + 1; }
     127   
     128    static const char* gprName(RegisterID id)
     129    {
     130        ASSERT(id >= firstRegister() && id <= lastRegister());
     131        static const char* const nameForRegister[numberOfRegisters()] = {
     132#if CPU(X86_64)
     133            "rax", "rcx", "rdx", "rbx",
     134            "rsp", "rbp", "rsi", "rdi",
     135            "r8", "r9", "r10", "r11",
     136            "r12", "r13", "r14", "r15"
     137#else
     138            "eax", "ecx", "edx", "ebx",
     139            "esp", "ebp", "esi", "edi",
     140#endif
     141        };
     142        return nameForRegister[id];
     143    }
     144
     145    static const char* sprName(SPRegisterID id)
     146    {
     147        ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
     148        static const char* const nameForRegister[numberOfSPRegisters()] = {
     149#if CPU(X86_64)
     150            "rip", "rflags"
     151#else
     152            "eip", "eflags"
     153#endif
     154        };
     155        return nameForRegister[id];
     156    }
     157   
     158    static const char* fprName(FPRegisterID reg)
     159    {
     160        ASSERT(reg >= firstFPRegister() && reg <= lastFPRegister());
     161        static const char* const nameForRegister[numberOfFPRegisters()] = {
     162            "xmm0", "xmm1", "xmm2", "xmm3",
     163            "xmm4", "xmm5", "xmm6", "xmm7",
     164#if CPU(X86_64)
     165            "xmm8", "xmm9", "xmm10", "xmm11",
     166            "xmm12", "xmm13", "xmm14", "xmm15"
     167#endif
     168        };
     169        return nameForRegister[reg];
     170    }
     171   
    149172    typedef enum {
    150173        ConditionO,
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