Changeset 224258 in webkit for trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h

Timestamp:

Oct 31, 2017, 4:12:32 PM (8 years ago)

Author:

[email protected]

Message:

Unreviewed, rolling out r224243, r224246, and r224248.
​https://bugs.webkit.org/show_bug.cgi?id=179083

The patch and fix broke the Windows build. (Requested by
mlewis13 on #webkit).

Reverted changesets:

"StructureStubInfo should have GPRReg members not int8_ts"
​https://bugs.webkit.org/show_bug.cgi?id=179071
​https://trac.webkit.org/changeset/224243

"Make all register enums be backed by uint8_t."
​https://bugs.webkit.org/show_bug.cgi?id=179074
​https://trac.webkit.org/changeset/224246

"Unreviewed, windows build fix."
​https://trac.webkit.org/changeset/224248

File:

• trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h (modified) (3 diffs)

trunk/Source/JavaScriptCore/assembler/ARM64Assembler.h

@@ -158 +158 @@
 namespace ARM64Registers {
 
-enum RegisterID : uint8_t {
+typedef enum {
     // Parameter/result registers.
     x0,
@@ -204 +204 @@
     x30 = lr,
     zr = 0x3f,
-};
-
-enum SPRegisterID : uint8_t {
+} RegisterID;
+
+typedef enum {
     pc,
     nzcv,
     fpsr
-};
+} SPRegisterID;
 
 // ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
 // and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
 // However, we only use them for 64-bit doubles.
-enum FPRegisterID : uint8_t {
+typedef enum {
     // Parameter/result registers.
     q0,
@@ -251 +251 @@
     q30,
     q31,
-};
+} FPRegisterID;
 
 static constexpr bool isSp(RegisterID reg) { return reg == sp; }