Changeset 254674 in webkit for trunk/Source/JavaScriptCore/offlineasm/mips.rb

Timestamp:

Jan 16, 2020, 5:21:07 AM (5 years ago)

Author:

Caio Lima

Message:

[JSC] 32-bit platforms should use a PC base register
​https://bugs.webkit.org/show_bug.cgi?id=203563

Reviewed by Keith Miller.

We are moving 32-bits LLInt implementation to follow the model useb by
64-bits architectures. It means that we now use PC and PB registers to
represent current Instruction. This patch will reduce the changes
we have from those architectures and mainly allow the usage of new
version of BytecodeIndex::m_packedBits. This also allow us remove
divergences on CallSiteIndex.
The change required the inclusion of a new callee-save register on
ARMv7 (r10), MIPS($s1) and CLOOP. Further changes necessary for
Baseline and DFG will come in a following patch.

• assembler/MIPSRegisters.h:
• interpreter/CallFrame.cpp:
• jit/GPRInfo.h:

(JSC::GPRInfo::toRegister):
(JSC::GPRInfo::toIndex):

• jit/RegisterSet.cpp:

(JSC::RegisterSet::vmCalleeSaveRegisters):
(JSC::RegisterSet::llintBaselineCalleeSaveRegisters):

• llint/LLIntData.h:
• llint/LLIntSlowPaths.cpp:

(JSC::LLInt::LLINT_SLOW_PATH_DECL):

• llint/LowLevelInterpreter.asm:
• llint/LowLevelInterpreter.cpp:

(JSC::CLoop::execute):

• llint/LowLevelInterpreter32_64.asm:
• llint/LowLevelInterpreter64.asm:
• offlineasm/arm.rb:
• offlineasm/mips.rb:

File:

• trunk/Source/JavaScriptCore/offlineasm/mips.rb (modified) (2 diffs)

trunk/Source/JavaScriptCore/offlineasm/mips.rb

@@ -44 +44 @@
 # $t9 =>            (stores the callee of a call opcode)
 # $gp =>            (globals)
+# $s0 => csr0       (callee-save, metadataTable)
+# $s1 => csr1       (callee-save, PB)
 # $s4 =>            (callee-save used to preserve $gp across calls)
 # $ra => lr
@@ -139 +141 @@
         when "csr0"
             "$s0"
+        when "csr1"
+            "$s1"
         when "lr"
             "$ra"