Changeset 292080 in webkit for trunk/Source/JavaScriptCore/offlineasm/arm.rb

Timestamp:

Mar 29, 2022, 4:21:12 PM (3 years ago)

Author:

[email protected]

Message:

[JSC][ARMv7] Cleanup GPR numbering
​https://bugs.webkit.org/show_bug.cgi?id=235027

Patch by Geza Lore <Geza Lore> on 2022-03-29
Reviewed by Yusuke Suzuki.

• Make the the lower order callee save register be regCS0/llint csr0.

Some of the CSR store/restore code relies on this and using a
numbering scheme consistent with other targets (that is: regCS<N> maps
to a lower number machine register than regCS<N+1>) eliminates some
ifdefs in LLInt, and hopefully will prevent hard to find issues due to
the mismatch from other targets that all follow this rule.

• In the Thumb-2 instruction set, use of r0-r7 can often be encoded

using a shorter, 16-bit instruction. Swap regT4/regT5 with
regT7/regT6, so lower order temporaries (which are usually used first)
map to the lower order registers that can yield denser code. This
then simplifies BaselineJITRegisters.h, and also saves about ~1% DFG
code size.

• In offlineasm, prefer low order registers for temporaries.

• Also clean up baseline instanceof op implementation.

• bytecode/StructureStubInfo.cpp:

(JSC::StructureStubInfo::initializeFromUnlinkedStructureStubInfo):

• jit/BaselineJITRegisters.h:
• jit/GPRInfo.h:

(JSC::GPRInfo::toIndex):
(JSC::PreferredArgumentImpl::preferredArgumentJSR):

• jit/JITOpcodes.cpp:

(JSC::JIT::emit_op_instanceof):
(JSC::JIT::emitSlow_op_instanceof):

• jit/JITPropertyAccess.cpp:

(JSC::JIT::emit_op_put_by_val):
(JSC::JIT::emitSlow_op_put_by_val):
(JSC::JIT::slow_op_put_by_val_callSlowOperationThenCheckExceptionGenerator):
(JSC::JIT::emit_op_put_private_name):
(JSC::JIT::emitSlow_op_put_private_name):
(JSC::JIT::slow_op_put_private_name_callSlowOperationThenCheckExceptionGenerator):

• llint/LowLevelInterpreter.asm:
• offlineasm/arm.rb:

File:

• trunk/Source/JavaScriptCore/offlineasm/arm.rb (modified) (3 diffs)

trunk/Source/JavaScriptCore/offlineasm/arm.rb

@@ -32 +32 @@
 #  x0 => t0, a0, r0
 #  x1 => t1, a1, r1
-#  x2 => t2, a2, r2
-#  x3 => t3, a3, r3
-#  x6 =>            (callee-save scratch)
+#  x2 => t2, a2
+#  x3 => t3, a3
+#  x4 => t4                 (callee-save, PC)
+#  x5 => t5                 (callee-save)
+#  x6 => scratch            (callee-save)
 #  x7 => cfr
-#  x8 => t4         (callee-save)
-#  x9 => t5         (callee-save)
-# x10 => csr1       (callee-save, PB)
-# x11 => cfr, csr0  (callee-save, metadataTable)
-# x12 =>            (callee-save scratch)
+#  x8 => t6                 (callee-save)
+#  x9 => t7, also scratch!  (callee-save)
+# x10 => csr0               (callee-save, metadataTable)
+# x11 => csr1               (callee-save, PB)
+# x12 => scratch            (callee-save)
 #  lr => lr
 #  sp => sp
@@ -70 +72 @@
 end
 
-ARM_EXTRA_GPRS = [SpecialRegister.new("r6"), SpecialRegister.new("r4"), SpecialRegister.new("r12")]
+# These are allocated from the end. Use the low order r6 first, ast it's often
+# cheaper to encode. r12 and r9 are equivalent, but r9 conflicts with t7, so r9
+# only as last resort.
+ARM_EXTRA_GPRS = [SpecialRegister.new("r9"), SpecialRegister.new("r12"), SpecialRegister.new("r6")]
 ARM_EXTRA_FPRS = [SpecialRegister.new("d7")]
 ARM_SCRATCH_FPR = SpecialRegister.new("d6")
@@ -100 +105 @@
         when "t2", "a2"
             "r2"
-        when "a3"
+        when "t3", "a3"
             "r3"
-        when "t3"
-            "r3"
-        when "t4"
-            "r8"
+        when "t4" # LLInt PC
+            "r4"
         when "t5"
-            "r9"
+            "r5"
         when "cfr"
             "r7"
+        when "t6"
+            "r8"
+        when "t7"
+            "r9" # r9 is also a scratch register, so use carefully!
         when "csr0"
+            "r10"
+        when "csr1"
             "r11"
-        when "csr1"
-            "r10"
         when "lr"
             "lr"