Ignore:
Timestamp:
May 11, 2009, 9:20:29 PM (16 years ago)
Author:
[email protected]
Message:

2009-05-11 Geoffrey Garen <​[email protected]>

Reviewed by Sam Weinig.


A little more JIT refactoring.


Rearranged code to more clearly indicate what's conditionally compiled
and why. Now, all shared code is at the top of our JIT files, and all
#if'd code is at the bottom. #if'd code is delineated by large comments.


Moved functions that relate to the JIT but don't explicitly do codegen
into JIT.cpp. Refactored SSE2 check to store its result as a data member
in the JIT.

  • jit/JIT.cpp: (JSC::isSSE2Present): (JSC::JIT::JIT): (JSC::JIT::unlinkCall): (JSC::JIT::linkCall):
  • jit/JIT.h: (JSC::JIT::isSSE2Present):
  • jit/JITArithmetic.cpp: (JSC::JIT::emit_op_mod): (JSC::JIT::emitSlow_op_mod):
  • jit/JITCall.cpp: (JSC::JIT::compileOpCallVarargs): (JSC::JIT::compileOpCallVarargsSlowCase):
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/JavaScriptCore/jit/JITArithmetic.cpp

    r43534 r43543  
    4646using namespace std;
    4747
    48 // All X86 Macs are guaranteed to support at least SSE2
    49 #if PLATFORM(X86_64) || (PLATFORM(X86) && PLATFORM(MAC))
    50 
    51 static inline bool isSSE2Present()
    52 {
    53     return true;
    54 }
    55 
    56 #else
    57 
    58 static bool isSSE2Present()
    59 {
    60     static const int SSE2FeatureBit = 1 << 26;
    61     struct SSE2Check {
    62         SSE2Check()
    63         {
    64             int flags;
    65 #if COMPILER(MSVC)
    66             _asm {
    67                 mov eax, 1 // cpuid function 1 gives us the standard feature set
    68                 cpuid;
    69                 mov flags, edx;
    70             }
    71 #elif COMPILER(GCC)
    72             asm (
    73                  "movl $0x1, %%eax;"
    74                  "pushl %%ebx;"
    75                  "cpuid;"
    76                  "popl %%ebx;"
    77                  "movl %%edx, %0;"
    78                  : "=g" (flags)
    79                  :
    80                  : "%eax", "%ecx", "%edx"
    81                  );
    82 #else
    83             flags = 0;
    84 #endif
    85             present = (flags & SSE2FeatureBit) != 0;
    86         }
    87         bool present;
    88     };
    89     static SSE2Check check;
    90     return check.present;
    91 }
    92 
    93 #endif
    94 
    9548namespace JSC {
    9649
    … …  
    12073    emitPutVirtualRegister(result);
    12174}
     75
    12276void JIT::emitSlow_op_lshift(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    12377{
    … …  
    278232    }
    279233}
     234
    280235void JIT::emitSlow_op_jnless(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    281236{
    … …  
    465420    }
    466421}
     422
    467423void JIT::emitSlow_op_jnlesseq(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    468424{
    … …  
    650606    emitPutVirtualRegister(result);
    651607}
     608
    652609void JIT::emitSlow_op_bitand(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    653610{
    … …  
    675632}
    676633
     634void JIT::emit_op_post_inc(Instruction* currentInstruction)
     635{
     636    unsigned result = currentInstruction[1].u.operand;
     637    unsigned srcDst = currentInstruction[2].u.operand;
     638
     639    emitGetVirtualRegister(srcDst, regT0);
     640    move(regT0, regT1);
     641    emitJumpSlowCaseIfNotImmediateInteger(regT0);
     642#if USE(ALTERNATE_JSIMMEDIATE)
     643    addSlowCase(branchAdd32(Overflow, Imm32(1), regT1));
     644    emitFastArithIntToImmNoCheck(regT1, regT1);
     645#else
     646    addSlowCase(branchAdd32(Overflow, Imm32(1 << JSImmediate::IntegerPayloadShift), regT1));
     647    signExtend32ToPtr(regT1, regT1);
     648#endif
     649    emitPutVirtualRegister(srcDst, regT1);
     650    emitPutVirtualRegister(result);
     651}
     652
     653void JIT::emitSlow_op_post_inc(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
     654{
     655    unsigned result = currentInstruction[1].u.operand;
     656    unsigned srcDst = currentInstruction[2].u.operand;
     657
     658    linkSlowCase(iter);
     659    linkSlowCase(iter);
     660    JITStubCall stubCall(this, JITStubs::cti_op_post_inc);
     661    stubCall.addArgument(regT0);
     662    stubCall.addArgument(Imm32(srcDst));
     663    stubCall.call(result);
     664}
     665
     666void JIT::emit_op_post_dec(Instruction* currentInstruction)
     667{
     668    unsigned result = currentInstruction[1].u.operand;
     669    unsigned srcDst = currentInstruction[2].u.operand;
     670
     671    emitGetVirtualRegister(srcDst, regT0);
     672    move(regT0, regT1);
     673    emitJumpSlowCaseIfNotImmediateInteger(regT0);
     674#if USE(ALTERNATE_JSIMMEDIATE)
     675    addSlowCase(branchSub32(Zero, Imm32(1), regT1));
     676    emitFastArithIntToImmNoCheck(regT1, regT1);
     677#else
     678    addSlowCase(branchSub32(Zero, Imm32(1 << JSImmediate::IntegerPayloadShift), regT1));
     679    signExtend32ToPtr(regT1, regT1);
     680#endif
     681    emitPutVirtualRegister(srcDst, regT1);
     682    emitPutVirtualRegister(result);
     683}
     684
     685void JIT::emitSlow_op_post_dec(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
     686{
     687    unsigned result = currentInstruction[1].u.operand;
     688    unsigned srcDst = currentInstruction[2].u.operand;
     689
     690    linkSlowCase(iter);
     691    linkSlowCase(iter);
     692    JITStubCall stubCall(this, JITStubs::cti_op_post_dec);
     693    stubCall.addArgument(regT0);
     694    stubCall.addArgument(Imm32(srcDst));
     695    stubCall.call(result);
     696}
     697
     698void JIT::emit_op_pre_inc(Instruction* currentInstruction)
     699{
     700    unsigned srcDst = currentInstruction[1].u.operand;
     701
     702    emitGetVirtualRegister(srcDst, regT0);
     703    emitJumpSlowCaseIfNotImmediateInteger(regT0);
     704#if USE(ALTERNATE_JSIMMEDIATE)
     705    addSlowCase(branchAdd32(Overflow, Imm32(1), regT0));
     706    emitFastArithIntToImmNoCheck(regT0, regT0);
     707#else
     708    addSlowCase(branchAdd32(Overflow, Imm32(1 << JSImmediate::IntegerPayloadShift), regT0));
     709    signExtend32ToPtr(regT0, regT0);
     710#endif
     711    emitPutVirtualRegister(srcDst);
     712}
     713
     714void JIT::emitSlow_op_pre_inc(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
     715{
     716    unsigned srcDst = currentInstruction[1].u.operand;
     717
     718    Jump notImm = getSlowCase(iter);
     719    linkSlowCase(iter);
     720    emitGetVirtualRegister(srcDst, regT0);
     721    notImm.link(this);
     722    JITStubCall stubCall(this, JITStubs::cti_op_pre_inc);
     723    stubCall.addArgument(regT0);
     724    stubCall.call(srcDst);
     725}
     726
     727void JIT::emit_op_pre_dec(Instruction* currentInstruction)
     728{
     729    unsigned srcDst = currentInstruction[1].u.operand;
     730
     731    emitGetVirtualRegister(srcDst, regT0);
     732    emitJumpSlowCaseIfNotImmediateInteger(regT0);
     733#if USE(ALTERNATE_JSIMMEDIATE)
     734    addSlowCase(branchSub32(Zero, Imm32(1), regT0));
     735    emitFastArithIntToImmNoCheck(regT0, regT0);
     736#else
     737    addSlowCase(branchSub32(Zero, Imm32(1 << JSImmediate::IntegerPayloadShift), regT0));
     738    signExtend32ToPtr(regT0, regT0);
     739#endif
     740    emitPutVirtualRegister(srcDst);
     741}
     742
     743void JIT::emitSlow_op_pre_dec(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
     744{
     745    unsigned srcDst = currentInstruction[1].u.operand;
     746
     747    Jump notImm = getSlowCase(iter);
     748    linkSlowCase(iter);
     749    emitGetVirtualRegister(srcDst, regT0);
     750    notImm.link(this);
     751    JITStubCall stubCall(this, JITStubs::cti_op_pre_dec);
     752    stubCall.addArgument(regT0);
     753    stubCall.call(srcDst);
     754}
     755
     756/* ------------------------------ BEGIN: OP_MOD ------------------------------ */
     757
    677758#if PLATFORM(X86) || PLATFORM(X86_64)
     759
    678760void JIT::emit_op_mod(Instruction* currentInstruction)
    679761{
    … …  
    699781    emitPutVirtualRegister(result);
    700782}
     783
    701784void JIT::emitSlow_op_mod(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    702785{
    … …  
    721804    stubCall.call(result);
    722805}
    723 #else
     806
     807#else // PLATFORM(X86) || PLATFORM(X86_64)
     808
    724809void JIT::emit_op_mod(Instruction* currentInstruction)
    725810{
    … …  
    733818    stubCall.call(result);
    734819}
     820
    735821void JIT::emitSlow_op_mod(Instruction*, Vector<SlowCaseEntry>::iterator&)
    736822{
    737823    ASSERT_NOT_REACHED();
    738824}
    739 #endif
    740 
    741 void JIT::emit_op_post_inc(Instruction* currentInstruction)
    742 {
    743     unsigned result = currentInstruction[1].u.operand;
    744     unsigned srcDst = currentInstruction[2].u.operand;
    745 
    746     emitGetVirtualRegister(srcDst, regT0);
    747     move(regT0, regT1);
    748     emitJumpSlowCaseIfNotImmediateInteger(regT0);
    749 #if USE(ALTERNATE_JSIMMEDIATE)
    750     addSlowCase(branchAdd32(Overflow, Imm32(1), regT1));
    751     emitFastArithIntToImmNoCheck(regT1, regT1);
    752 #else
    753     addSlowCase(branchAdd32(Overflow, Imm32(1 << JSImmediate::IntegerPayloadShift), regT1));
    754     signExtend32ToPtr(regT1, regT1);
    755 #endif
    756     emitPutVirtualRegister(srcDst, regT1);
    757     emitPutVirtualRegister(result);
    758 }
    759 
    760 void JIT::emitSlow_op_post_inc(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    761 {
    762     unsigned result = currentInstruction[1].u.operand;
    763     unsigned srcDst = currentInstruction[2].u.operand;
    764 
    765     linkSlowCase(iter);
    766     linkSlowCase(iter);
    767     JITStubCall stubCall(this, JITStubs::cti_op_post_inc);
    768     stubCall.addArgument(regT0);
    769     stubCall.addArgument(Imm32(srcDst));
    770     stubCall.call(result);
    771 }
    772 
    773 void JIT::emit_op_post_dec(Instruction* currentInstruction)
    774 {
    775     unsigned result = currentInstruction[1].u.operand;
    776     unsigned srcDst = currentInstruction[2].u.operand;
    777 
    778     emitGetVirtualRegister(srcDst, regT0);
    779     move(regT0, regT1);
    780     emitJumpSlowCaseIfNotImmediateInteger(regT0);
    781 #if USE(ALTERNATE_JSIMMEDIATE)
    782     addSlowCase(branchSub32(Zero, Imm32(1), regT1));
    783     emitFastArithIntToImmNoCheck(regT1, regT1);
    784 #else
    785     addSlowCase(branchSub32(Zero, Imm32(1 << JSImmediate::IntegerPayloadShift), regT1));
    786     signExtend32ToPtr(regT1, regT1);
    787 #endif
    788     emitPutVirtualRegister(srcDst, regT1);
    789     emitPutVirtualRegister(result);
    790 }
    791 void JIT::emitSlow_op_post_dec(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    792 {
    793     unsigned result = currentInstruction[1].u.operand;
    794     unsigned srcDst = currentInstruction[2].u.operand;
    795 
    796     linkSlowCase(iter);
    797     linkSlowCase(iter);
    798     JITStubCall stubCall(this, JITStubs::cti_op_post_dec);
    799     stubCall.addArgument(regT0);
    800     stubCall.addArgument(Imm32(srcDst));
    801     stubCall.call(result);
    802 }
    803 
    804 void JIT::emit_op_pre_inc(Instruction* currentInstruction)
    805 {
    806     unsigned srcDst = currentInstruction[1].u.operand;
    807 
    808     emitGetVirtualRegister(srcDst, regT0);
    809     emitJumpSlowCaseIfNotImmediateInteger(regT0);
    810 #if USE(ALTERNATE_JSIMMEDIATE)
    811     addSlowCase(branchAdd32(Overflow, Imm32(1), regT0));
    812     emitFastArithIntToImmNoCheck(regT0, regT0);
    813 #else
    814     addSlowCase(branchAdd32(Overflow, Imm32(1 << JSImmediate::IntegerPayloadShift), regT0));
    815     signExtend32ToPtr(regT0, regT0);
    816 #endif
    817     emitPutVirtualRegister(srcDst);
    818 }
    819 void JIT::emitSlow_op_pre_inc(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    820 {
    821     unsigned srcDst = currentInstruction[1].u.operand;
    822 
    823     Jump notImm = getSlowCase(iter);
    824     linkSlowCase(iter);
    825     emitGetVirtualRegister(srcDst, regT0);
    826     notImm.link(this);
    827     JITStubCall stubCall(this, JITStubs::cti_op_pre_inc);
    828     stubCall.addArgument(regT0);
    829     stubCall.call(srcDst);
    830 }
    831 
    832 void JIT::emit_op_pre_dec(Instruction* currentInstruction)
    833 {
    834     unsigned srcDst = currentInstruction[1].u.operand;
    835 
    836     emitGetVirtualRegister(srcDst, regT0);
    837     emitJumpSlowCaseIfNotImmediateInteger(regT0);
    838 #if USE(ALTERNATE_JSIMMEDIATE)
    839     addSlowCase(branchSub32(Zero, Imm32(1), regT0));
    840     emitFastArithIntToImmNoCheck(regT0, regT0);
    841 #else
    842     addSlowCase(branchSub32(Zero, Imm32(1 << JSImmediate::IntegerPayloadShift), regT0));
    843     signExtend32ToPtr(regT0, regT0);
    844 #endif
    845     emitPutVirtualRegister(srcDst);
    846 }
    847 void JIT::emitSlow_op_pre_dec(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    848 {
    849     unsigned srcDst = currentInstruction[1].u.operand;
    850 
    851     Jump notImm = getSlowCase(iter);
    852     linkSlowCase(iter);
    853     emitGetVirtualRegister(srcDst, regT0);
    854     notImm.link(this);
    855     JITStubCall stubCall(this, JITStubs::cti_op_pre_dec);
    856     stubCall.addArgument(regT0);
    857     stubCall.call(srcDst);
    858 }
    859 
     825
     826#endif // PLATFORM(X86) || PLATFORM(X86_64)
     827
     828/* ------------------------------ END: OP_MOD ------------------------------ */
    860829
    861830#if !ENABLE(JIT_OPTIMIZE_ARITHMETIC)
     831
     832/* ------------------------------ BEGIN: !ENABLE(JIT_OPTIMIZE_ARITHMETIC) (OP_ADD, OP_SUB, OP_MUL) ------------------------------ */
    862833
    863834void JIT::emit_op_add(Instruction* currentInstruction)
    … …  
    913884
    914885#elif USE(ALTERNATE_JSIMMEDIATE) // *AND* ENABLE(JIT_OPTIMIZE_ARITHMETIC)
     886
     887/* ------------------------------ BEGIN: USE(ALTERNATE_JSIMMEDIATE) (OP_ADD, OP_SUB, OP_MUL) ------------------------------ */
    915888
    916889void JIT::compileBinaryArithOp(OpcodeID opcodeID, unsigned, unsigned op1, unsigned op2, OperandTypes)
    … …  
    1018991    emitPutVirtualRegister(result);
    1019992}
     993
    1020994void JIT::emitSlow_op_add(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    1021995{
    … …  
    10591033    emitPutVirtualRegister(result);
    10601034}
     1035
    10611036void JIT::emitSlow_op_mul(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    10621037{
    … …  
    10901065    emitPutVirtualRegister(result);
    10911066}
     1067
    10921068void JIT::emitSlow_op_sub(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    10931069{
    … …  
    11001076}
    11011077
    1102 #else
     1078#else // !ENABLE(JIT_OPTIMIZE_ARITHMETIC)
     1079
     1080/* ------------------------------ BEGIN: !ENABLE(JIT_OPTIMIZE_ARITHMETIC) (OP_ADD, OP_SUB, OP_MUL) ------------------------------ */
    11031081
    11041082typedef X86Assembler::JmpSrc JmpSrc;
    … …  
    14061384    compileBinaryArithOp(op_sub, currentInstruction[1].u.operand, currentInstruction[2].u.operand, currentInstruction[3].u.operand, OperandTypes::fromInt(currentInstruction[4].u.operand));
    14071385}
     1386
    14081387void JIT::emitSlow_op_sub(Instruction* currentInstruction, Vector<SlowCaseEntry>::iterator& iter)
    14091388{
    … …  
    14111390}
    14121391
    1413 #endif
     1392#endif // !ENABLE(JIT_OPTIMIZE_ARITHMETIC)
     1393
     1394/* ------------------------------ END: OP_ADD, OP_SUB, OP_MUL ------------------------------ */
    14141395
    14151396} // namespace JSC
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