Ignore:
Timestamp:
Aug 19, 2009, 5:02:24 PM (16 years ago)
Author:
[email protected]
Message:

2009-08-19 Yong Li <​[email protected]>

Reviewed by Gavin Barraclough.

Change namespace ARM to ARMRegisters
X86 to X86Registers to avoid conflict with macros
​https://bugs.webkit.org/show_bug.cgi?id=28428

  • assembler/ARMAssembler.cpp:
  • assembler/ARMAssembler.h:
  • assembler/ARMv7Assembler.h:
  • assembler/MacroAssemblerARM.h:
  • assembler/MacroAssemblerARMv7.h:
  • assembler/MacroAssemblerX86Common.h:
  • assembler/MacroAssemblerX86_64.h:
  • assembler/X86Assembler.h:
  • jit/JIT.h:
  • jit/JITArithmetic.cpp:
  • jit/JITInlineMethods.h:
  • jit/JITOpcodes.cpp:
  • wrec/WRECGenerator.cpp:
  • wrec/WRECGenerator.h:
  • yarr/RegexJIT.cpp:
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/JavaScriptCore/assembler/ARMv7Assembler.h

    r47186 r47530  
    3838namespace JSC {
    3939
    40 namespace ARM {
     40namespace ARMRegisters {
    4141    typedef enum {
    4242        r0,
    … …  
    408408class ARMv7Assembler {
    409409public:
    410     typedef ARM::RegisterID RegisterID;
    411     typedef ARM::FPRegisterID FPRegisterID;
     410    typedef ARMRegisters::RegisterID RegisterID;
     411    typedef ARMRegisters::FPRegisterID FPRegisterID;
    412412
    413413    // (HS, LO, HI, LS) -> (AE, B, A, BE)
    … …  
    481481    bool BadReg(RegisterID reg)
    482482    {
    483         return (reg == ARM::sp) || (reg == ARM::pc);
     483        return (reg == ARMRegisters::sp) || (reg == ARMRegisters::pc);
    484484    }
    485485
    … …  
    693693    {
    694694        // Rd can only be SP if Rn is also SP.
    695         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    696         ASSERT(rd != ARM::pc);
    697         ASSERT(rn != ARM::pc);
     695        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     696        ASSERT(rd != ARMRegisters::pc);
     697        ASSERT(rn != ARMRegisters::pc);
    698698        ASSERT(imm.isValid());
    699699
    700         if (rn == ARM::sp) {
     700        if (rn == ARMRegisters::sp) {
    701701            if (!(rd & 8) && imm.isUInt10()) {
    702702                m_formatter.oneWordOp5Reg3Imm8(OP_ADD_SP_imm_T1, rd, imm.getUInt10() >> 2);
    703703                return;
    704             } else if ((rd == ARM::sp) && imm.isUInt9()) {
     704            } else if ((rd == ARMRegisters::sp) && imm.isUInt9()) {
    705705                m_formatter.oneWordOp9Imm7(OP_ADD_SP_imm_T2, imm.getUInt9() >> 2);
    706706                return;
    … …  
    726726    void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
    727727    {
    728         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    729         ASSERT(rd != ARM::pc);
    730         ASSERT(rn != ARM::pc);
     728        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     729        ASSERT(rd != ARMRegisters::pc);
     730        ASSERT(rn != ARMRegisters::pc);
    731731        ASSERT(!BadReg(rm));
    732732        m_formatter.twoWordOp12Reg4FourFours(OP_ADD_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
    … …  
    750750    {
    751751        // Rd can only be SP if Rn is also SP.
    752         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    753         ASSERT(rd != ARM::pc);
    754         ASSERT(rn != ARM::pc);
     752        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     753        ASSERT(rd != ARMRegisters::pc);
     754        ASSERT(rn != ARMRegisters::pc);
    755755        ASSERT(imm.isEncodedImm());
    756756
    … …  
    771771    void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
    772772    {
    773         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    774         ASSERT(rd != ARM::pc);
    775         ASSERT(rn != ARM::pc);
     773        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     774        ASSERT(rd != ARMRegisters::pc);
     775        ASSERT(rn != ARMRegisters::pc);
    776776        ASSERT(!BadReg(rm));
    777777        m_formatter.twoWordOp12Reg4FourFours(OP_ADD_S_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
    … …  
    839839    JmpSrc blx(RegisterID rm)
    840840    {
    841         ASSERT(rm != ARM::pc);
     841        ASSERT(rm != ARMRegisters::pc);
    842842        m_formatter.oneWordOp8RegReg143(OP_BLX, rm, (RegisterID)8);
    843843        return JmpSrc(m_formatter.size());
    … …  
    858858    void cmn(RegisterID rn, ARMThumbImmediate imm)
    859859    {
    860         ASSERT(rn != ARM::pc);
     860        ASSERT(rn != ARMRegisters::pc);
    861861        ASSERT(imm.isEncodedImm());
    862862
    … …  
    866866    void cmp(RegisterID rn, ARMThumbImmediate imm)
    867867    {
    868         ASSERT(rn != ARM::pc);
     868        ASSERT(rn != ARMRegisters::pc);
    869869        ASSERT(imm.isEncodedImm());
    870870
    … …  
    877877    void cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
    878878    {
    879         ASSERT(rn != ARM::pc);
     879        ASSERT(rn != ARMRegisters::pc);
    880880        ASSERT(!BadReg(rm));
    881881        m_formatter.twoWordOp12Reg4FourFours(OP_CMP_reg_T2, rn, FourFours(shift.hi4(), 0xf, shift.lo4(), rm));
    … …  
    939939    }
    940940
    941     // rt == ARM::pc only allowed if last instruction in IT (if then) block.
     941    // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
    942942    void ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
    943943    {
    944         ASSERT(rn != ARM::pc); // LDR (literal)
     944        ASSERT(rn != ARMRegisters::pc); // LDR (literal)
    945945        ASSERT(imm.isUInt12());
    946946
    947947        if (!((rt | rn) & 8) && imm.isUInt7())
    948948            m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDR_imm_T1, imm.getUInt7() >> 2, rn, rt);
    949         else if ((rn == ARM::sp) && !(rt & 8) && imm.isUInt10())
     949        else if ((rn == ARMRegisters::sp) && !(rt & 8) && imm.isUInt10())
    950950            m_formatter.oneWordOp5Reg3Imm8(OP_LDR_imm_T2, rt, imm.getUInt10() >> 2);
    951951        else
    … …  
    966966    void ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
    967967    {
    968         ASSERT(rt != ARM::pc);
    969         ASSERT(rn != ARM::pc);
     968        ASSERT(rt != ARMRegisters::pc);
     969        ASSERT(rn != ARMRegisters::pc);
    970970        ASSERT(index || wback);
    971971        ASSERT(!wback | (rt != rn));
    … …  
    986986    }
    987987
    988     // rt == ARM::pc only allowed if last instruction in IT (if then) block.
     988    // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
    989989    void ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)
    990990    {
    991         ASSERT(rn != ARM::pc); // LDR (literal)
     991        ASSERT(rn != ARMRegisters::pc); // LDR (literal)
    992992        ASSERT(!BadReg(rm));
    993993        ASSERT(shift <= 3);
    … …  
    999999    }
    10001000
    1001     // rt == ARM::pc only allowed if last instruction in IT (if then) block.
     1001    // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
    10021002    void ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
    10031003    {
    1004         ASSERT(rn != ARM::pc); // LDR (literal)
     1004        ASSERT(rn != ARMRegisters::pc); // LDR (literal)
    10051005        ASSERT(imm.isUInt12());
    10061006
    … …  
    10241024    void ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
    10251025    {
    1026         ASSERT(rt != ARM::pc);
    1027         ASSERT(rn != ARM::pc);
     1026        ASSERT(rt != ARMRegisters::pc);
     1027        ASSERT(rn != ARMRegisters::pc);
    10281028        ASSERT(index || wback);
    10291029        ASSERT(!wback | (rt != rn));
    … …  
    10471047    {
    10481048        ASSERT(!BadReg(rt));   // Memory hint
    1049         ASSERT(rn != ARM::pc); // LDRH (literal)
     1049        ASSERT(rn != ARMRegisters::pc); // LDRH (literal)
    10501050        ASSERT(!BadReg(rm));
    10511051        ASSERT(shift <= 3);
    … …  
    11981198    }
    11991199
    1200     // rt == ARM::pc only allowed if last instruction in IT (if then) block.
     1200    // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
    12011201    void str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
    12021202    {
    1203         ASSERT(rt != ARM::pc);
    1204         ASSERT(rn != ARM::pc);
     1203        ASSERT(rt != ARMRegisters::pc);
     1204        ASSERT(rn != ARMRegisters::pc);
    12051205        ASSERT(imm.isUInt12());
    12061206
    12071207        if (!((rt | rn) & 8) && imm.isUInt7())
    12081208            m_formatter.oneWordOp5Imm5Reg3Reg3(OP_STR_imm_T1, imm.getUInt7() >> 2, rn, rt);
    1209         else if ((rn == ARM::sp) && !(rt & 8) && imm.isUInt10())
     1209        else if ((rn == ARMRegisters::sp) && !(rt & 8) && imm.isUInt10())
    12101210            m_formatter.oneWordOp5Reg3Imm8(OP_STR_imm_T2, rt, imm.getUInt10() >> 2);
    12111211        else
    … …  
    12261226    void str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
    12271227    {
    1228         ASSERT(rt != ARM::pc);
    1229         ASSERT(rn != ARM::pc);
     1228        ASSERT(rt != ARMRegisters::pc);
     1229        ASSERT(rn != ARMRegisters::pc);
    12301230        ASSERT(index || wback);
    12311231        ASSERT(!wback | (rt != rn));
    … …  
    12461246    }
    12471247
    1248     // rt == ARM::pc only allowed if last instruction in IT (if then) block.
     1248    // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
    12491249    void str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)
    12501250    {
    1251         ASSERT(rn != ARM::pc);
     1251        ASSERT(rn != ARMRegisters::pc);
    12521252        ASSERT(!BadReg(rm));
    12531253        ASSERT(shift <= 3);
    … …  
    12621262    {
    12631263        // Rd can only be SP if Rn is also SP.
    1264         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    1265         ASSERT(rd != ARM::pc);
    1266         ASSERT(rn != ARM::pc);
     1264        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     1265        ASSERT(rd != ARMRegisters::pc);
     1266        ASSERT(rn != ARMRegisters::pc);
    12671267        ASSERT(imm.isValid());
    12681268
    1269         if ((rn == ARM::sp) && (rd == ARM::sp) && imm.isUInt9()) {
     1269        if ((rn == ARMRegisters::sp) && (rd == ARMRegisters::sp) && imm.isUInt9()) {
    12701270            m_formatter.oneWordOp9Imm7(OP_SUB_SP_imm_T1, imm.getUInt9() >> 2);
    12711271            return;
    … …  
    12901290    void sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
    12911291    {
    1292         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    1293         ASSERT(rd != ARM::pc);
    1294         ASSERT(rn != ARM::pc);
     1292        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     1293        ASSERT(rd != ARMRegisters::pc);
     1294        ASSERT(rn != ARMRegisters::pc);
    12951295        ASSERT(!BadReg(rm));
    12961296        m_formatter.twoWordOp12Reg4FourFours(OP_SUB_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
    … …  
    13101310    {
    13111311        // Rd can only be SP if Rn is also SP.
    1312         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    1313         ASSERT(rd != ARM::pc);
    1314         ASSERT(rn != ARM::pc);
     1312        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     1313        ASSERT(rd != ARMRegisters::pc);
     1314        ASSERT(rn != ARMRegisters::pc);
    13151315        ASSERT(imm.isValid());
    13161316
    1317         if ((rn == ARM::sp) && (rd == ARM::sp) && imm.isUInt9()) {
     1317        if ((rn == ARMRegisters::sp) && (rd == ARMRegisters::sp) && imm.isUInt9()) {
    13181318            m_formatter.oneWordOp9Imm7(OP_SUB_SP_imm_T1, imm.getUInt9() >> 2);
    13191319            return;
    … …  
    13341334    void sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
    13351335    {
    1336         ASSERT((rd != ARM::sp) || (rn == ARM::sp));
    1337         ASSERT(rd != ARM::pc);
    1338         ASSERT(rn != ARM::pc);
     1336        ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
     1337        ASSERT(rd != ARMRegisters::pc);
     1338        ASSERT(rn != ARMRegisters::pc);
    13391339        ASSERT(!BadReg(rm));
    13401340        m_formatter.twoWordOp12Reg4FourFours(OP_SUB_S_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
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