Changeset 48782 in webkit for trunk/JavaScriptCore/assembler/MacroAssemblerX86Common.h

Timestamp:

Sep 25, 2009, 7:27:02 PM (16 years ago)

Author:

[email protected]

Message:

2009-09-25 Gabor Loki <​[email protected]>

Reviewed by Gavin Barraclough.

Fix unaligned data access in YARR_JIT on ARMv5 and below.
​https://bugs.webkit.org/show_bug.cgi?id=29695

On ARMv5 and below all data access should be naturally aligned.
In the YARR_JIT there is a case when character pairs are
loaded from the input string, but this data access is not
naturally aligned. This fix introduces load32WithUnalignedHalfWords
and branch32WithUnalignedHalfWords functions which contain
naturally aligned memory loads - half word loads - on ARMv5 and below.

• assembler/MacroAssemblerARM.cpp: (JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):
• assembler/MacroAssemblerARM.h: (JSC::MacroAssemblerARM::load32WithUnalignedHalfWords): (JSC::MacroAssemblerARM::branch32WithUnalignedHalfWords):
• assembler/MacroAssemblerARMv7.h: (JSC::MacroAssemblerARMv7::load32WithUnalignedHalfWords): (JSC::MacroAssemblerARMv7::branch32): (JSC::MacroAssemblerARMv7::branch32WithUnalignedHalfWords):
• assembler/MacroAssemblerX86Common.h: (JSC::MacroAssemblerX86Common::load32WithUnalignedHalfWords): (JSC::MacroAssemblerX86Common::branch32WithUnalignedHalfWords):
• wtf/Platform.h:
• yarr/RegexJIT.cpp: (JSC::Yarr::RegexGenerator::generatePatternCharacterPair):

File:

• trunk/JavaScriptCore/assembler/MacroAssemblerX86Common.h (modified) (2 diffs)

trunk/JavaScriptCore/assembler/MacroAssemblerX86Common.h

@@ -307 +307 @@
     }
 
+    void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
+    {
+        load32(address, dest);
+    }
+
     DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
     {
@@ -603 +608 @@
         m_assembler.cmpl_im(right.m_value, left.offset, left.base, left.index, left.scale);
         return Jump(m_assembler.jCC(x86Condition(cond)));
+    }
+
+    Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, Imm32 right)
+    {
+        return branch32(cond, left, right);
     }