Changeset 52729 in webkit for trunk/JavaScriptCore/assembler/X86Assembler.h

Timestamp:

Jan 4, 2010, 3:38:56 AM (15 years ago)

Author:

[email protected]

Message:

2010-01-04 Maciej Stachowiak <​[email protected]>

Reviewed by Adam Barth.

Reorganize, document and rename CPU() platform macros.
​https://bugs.webkit.org/show_bug.cgi?id=33145
ExecutableAllocatorSymbian appears to have buggy ARM version check
​https://bugs.webkit.org/show_bug.cgi?id=33138

• wtf/Platform.h: Rename all macros related to detection of particular CPUs or classes of CPUs to CPU(), reorganize and document them.

All remaining changes are adapting to the renames, plus fixing the
second bug cited above.

• assembler/ARMAssembler.cpp:
• assembler/ARMAssembler.h:
• assembler/ARMv7Assembler.h:
• assembler/AbstractMacroAssembler.h: (JSC::AbstractMacroAssembler::Imm32::Imm32):
• assembler/MacroAssembler.h:
• assembler/MacroAssemblerARM.cpp:
• assembler/MacroAssemblerARM.h:
• assembler/MacroAssemblerCodeRef.h: (JSC::MacroAssemblerCodePtr::MacroAssemblerCodePtr):
• assembler/MacroAssemblerX86.h:
• assembler/MacroAssemblerX86Common.h:
• assembler/MacroAssemblerX86_64.h:
• assembler/X86Assembler.h: (JSC::X86Registers::): (JSC::X86Assembler::): (JSC::X86Assembler::movl_mEAX): (JSC::X86Assembler::movl_EAXm): (JSC::X86Assembler::repatchLoadPtrToLEA): (JSC::X86Assembler::X86InstructionFormatter::memoryModRM):
• jit/ExecutableAllocator.h:
• jit/ExecutableAllocatorFixedVMPool.cpp:
• jit/ExecutableAllocatorPosix.cpp:
• jit/ExecutableAllocatorSymbian.cpp: (JSC::ExecutableAllocator::intializePageSize):
• jit/JIT.cpp:
• jit/JIT.h:
• jit/JITArithmetic.cpp:
• jit/JITInlineMethods.h: (JSC::JIT::beginUninterruptedSequence): (JSC::JIT::restoreArgumentReferenceForTrampoline): (JSC::JIT::emitCount):
• jit/JITOpcodes.cpp: (JSC::JIT::privateCompileCTIMachineTrampolines):
• jit/JITPropertyAccess.cpp: (JSC::JIT::privateCompileGetByIdProto): (JSC::JIT::privateCompileGetByIdProtoList): (JSC::JIT::privateCompileGetByIdChainList): (JSC::JIT::privateCompileGetByIdChain):
• jit/JITStubs.cpp: (JSC::JITThunks::JITThunks):
• jit/JITStubs.h:
• runtime/Collector.cpp: (JSC::currentThreadStackBase): (JSC::getPlatformThreadRegisters): (JSC::otherThreadStackPointer):
• wrec/WREC.h:
• wrec/WRECGenerator.cpp: (JSC::WREC::Generator::generateEnter): (JSC::WREC::Generator::generateReturnSuccess): (JSC::WREC::Generator::generateReturnFailure):
• wrec/WRECGenerator.h:
• wtf/FastMalloc.cpp:
• wtf/TCSpinLock.h: (TCMalloc_SpinLock::Lock): (TCMalloc_SpinLock::Unlock): (TCMalloc_SlowLock):
• wtf/Threading.h:
• wtf/dtoa.cpp:
• yarr/RegexJIT.cpp: (JSC::Yarr::RegexGenerator::generateEnter): (JSC::Yarr::RegexGenerator::generateReturn):
• yarr/RegexJIT.h:

2010-01-04 Maciej Stachowiak <​[email protected]>

Reviewed by Adam Barth.

Reorganize, document and rename CPU() platform macros.
​https://bugs.webkit.org/show_bug.cgi?id=33145

• webkit/webkitwebsettings.cpp: (webkit_get_user_agent):

2010-01-04 Maciej Stachowiak <​[email protected]>

Reviewed by Adam Barth.

Reorganize, document and rename CPU() platform macros.
​https://bugs.webkit.org/show_bug.cgi?id=33145

• page/NavigatorBase.cpp:
• platform/text/AtomicString.cpp: (WebCore::equal):
• platform/text/StringHash.h: (WebCore::StringHash::equal):

File:

• trunk/JavaScriptCore/assembler/X86Assembler.h (modified) (31 diffs)

trunk/JavaScriptCore/assembler/X86Assembler.h

@@ -29 +29 @@
 #include <wtf/Platform.h>
 
-#if ENABLE(ASSEMBLER) && (PLATFORM(X86) || PLATFORM(X86_64))
+#if ENABLE(ASSEMBLER) && (CPU(X86) || CPU(X86_64))
 
 #include "AssemblerBuffer.h"
@@ -51 +51 @@
         edi,
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         r8,
         r9,
@@ -119 +119 @@
         OP_CMP_EvGv                     = 0x39,
         OP_CMP_GvEv                     = 0x3B,
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         PRE_REX                         = 0x40,
 #endif
         OP_PUSH_EAX                     = 0x50,
         OP_POP_EAX                      = 0x58,
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         OP_MOVSXD_GvEv                  = 0x63,
 #endif
@@ -297 +297 @@
     // Arithmetic operations:
 
-#if !PLATFORM(X86_64)
+#if !CPU(X86_64)
     void adcl_im(int imm, void* addr)
     {
@@ -347 +347 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void addq_rr(RegisterID src, RegisterID dst)
     {
@@ -424 +424 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void andq_rr(RegisterID src, RegisterID dst)
     {
@@ -510 +510 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void orq_rr(RegisterID src, RegisterID dst)
     {
@@ -576 +576 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void subq_rr(RegisterID src, RegisterID dst)
     {
@@ -642 +642 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void xorq_rr(RegisterID src, RegisterID dst)
     {
@@ -690 +690 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void sarq_CLr(RegisterID dst)
     {
@@ -790 +790 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void cmpq_rr(RegisterID src, RegisterID dst)
     {
@@ -898 +898 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void testq_rr(RegisterID src, RegisterID dst)
     {
@@ -972 +972 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void xchgq_rr(RegisterID src, RegisterID dst)
     {
@@ -1002 +1002 @@
     {
         m_formatter.oneByteOp(OP_MOV_EAXOv);
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
 #else
@@ -1039 +1039 @@
     {
         m_formatter.oneByteOp(OP_MOV_OvEAX);
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
 #else
@@ -1046 +1046 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void movq_rr(RegisterID src, RegisterID dst)
     {
@@ -1158 +1158 @@
         m_formatter.oneByteOp(OP_LEA, dst, base, offset);
     }
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void leaq_mr(int offset, RegisterID base, RegisterID dst)
     {
@@ -1324 +1324 @@
     }
 
-#if !PLATFORM(X86_64)
+#if !CPU(X86_64)
     void cvtsi2sd_mr(void* address, XMMRegisterID dst)
     {
@@ -1344 +1344 @@
     }
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
     void movq_rr(XMMRegisterID src, RegisterID dst)
     {
@@ -1370 +1370 @@
     }
 
-#if !PLATFORM(X86_64)
+#if !CPU(X86_64)
     void movsd_mr(void* address, XMMRegisterID dst)
     {
@@ -1536 +1536 @@
     static void repatchLoadPtrToLEA(void* where)
     {
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         // On x86-64 pointer memory accesses require a 64-bit operand, and as such a REX prefix.
         // Skip over the prefix byte.
@@ -1680 +1680 @@
         }
 
-#if !PLATFORM(X86_64)
+#if !CPU(X86_64)
         void oneByteOp(OneByteOpcodeID opcode, int reg, void* address)
         {
@@ -1723 +1723 @@
         }
 
-#if !PLATFORM(X86_64)
+#if !CPU(X86_64)
         void twoByteOp(TwoByteOpcodeID opcode, int reg, void* address)
         {
@@ -1733 +1733 @@
 #endif
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         // Quad-word-sized operands:
         //
@@ -1892 +1892 @@
         static const RegisterID hasSib = X86Registers::esp;
         static const RegisterID noIndex = X86Registers::esp;
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
         static const RegisterID noBase2 = X86Registers::r13;
         static const RegisterID hasSib2 = X86Registers::r12;
@@ -1968 +1968 @@
         {
             // A base of esp or r12 would be interpreted as a sib, so force a sib with no index & put the base in there.
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
             if ((base == hasSib) || (base == hasSib2)) {
 #else
@@ -1983 +1983 @@
                 }
             } else {
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
                 if (!offset && (base != noBase) && (base != noBase2))
 #else
@@ -2002 +2002 @@
         {
             // A base of esp or r12 would be interpreted as a sib, so force a sib with no index & put the base in there.
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
             if ((base == hasSib) || (base == hasSib2)) {
 #else
@@ -2019 +2019 @@
             ASSERT(index != noIndex);
 
-#if PLATFORM(X86_64)
+#if CPU(X86_64)
             if (!offset && (base != noBase) && (base != noBase2))
 #else
@@ -2034 +2034 @@
         }
 
-#if !PLATFORM(X86_64)
+#if !CPU(X86_64)
         void memoryModRM(int reg, void* address)
         {
@@ -2049 +2049 @@
 } // namespace JSC
 
-#endif // ENABLE(ASSEMBLER) && PLATFORM(X86)
+#endif // ENABLE(ASSEMBLER) && CPU(X86)
 
 #endif // X86Assembler_h