Changeset 62306 in webkit for trunk/JavaScriptCore/assembler/MacroAssemblerARMv7.h

Timestamp:

Jul 1, 2010, 3:56:58 PM (15 years ago)

Author:

[email protected]

Message:

Bug 41490 - Add missing operations to MacroAssemblerARMv7
Also, make single, double, quad register numbers in ARMv7Assembler distinct & strongly typed.

Reviewed by Oliver Hunt.

• assembler/ARMv7Assembler.h:

(JSC::ARMRegisters::):
(JSC::ARMRegisters::asSingle):
(JSC::ARMRegisters::asDouble):
(JSC::VFPImmediate::VFPImmediate):
(JSC::VFPImmediate::isValid):
(JSC::VFPImmediate::value):
(JSC::ARMv7Assembler::singleRegisterMask):
(JSC::ARMv7Assembler::doubleRegisterMask):
(JSC::ARMv7Assembler::):
(JSC::ARMv7Assembler::add_S):
(JSC::ARMv7Assembler::neg):
(JSC::ARMv7Assembler::orr_S):
(JSC::ARMv7Assembler::sub):
(JSC::ARMv7Assembler::sub_S):
(JSC::ARMv7Assembler::vadd_F64):
(JSC::ARMv7Assembler::vcmp_F64):
(JSC::ARMv7Assembler::vcvt_F64_S32):
(JSC::ARMv7Assembler::vcvtr_S32_F64):
(JSC::ARMv7Assembler::vdiv_F64):
(JSC::ARMv7Assembler::vldr):
(JSC::ARMv7Assembler::vmov_F64_0):
(JSC::ARMv7Assembler::vmov):
(JSC::ARMv7Assembler::vmul_F64):
(JSC::ARMv7Assembler::vstr):
(JSC::ARMv7Assembler::vsub_F64):
(JSC::ARMv7Assembler::vcvt):
(JSC::ARMv7Assembler::vmem):

• assembler/AbstractMacroAssembler.h:
• assembler/MacroAssemblerARM.h:
• assembler/MacroAssemblerARMv7.h:

(JSC::MacroAssemblerARMv7::fpTempRegisterAsSingle):
(JSC::MacroAssemblerARMv7::neg32):
(JSC::MacroAssemblerARMv7::loadDouble):
(JSC::MacroAssemblerARMv7::divDouble):
(JSC::MacroAssemblerARMv7::convertInt32ToDouble):
(JSC::MacroAssemblerARMv7::branchConvertDoubleToInt32):
(JSC::MacroAssemblerARMv7::zeroDouble):
(JSC::MacroAssemblerARMv7::branchOr32):
(JSC::MacroAssemblerARMv7::set32):
(JSC::MacroAssemblerARMv7::set8):

• assembler/MacroAssemblerMIPS.h:
• assembler/MacroAssemblerX86Common.h:

File:

• trunk/JavaScriptCore/assembler/MacroAssemblerARMv7.h (modified) (10 diffs)

trunk/JavaScriptCore/assembler/MacroAssemblerARMv7.h

@@ -39 +39 @@
     //        - dTR is likely used more than aTR, and we'll get better instruction
     //        encoding if it's in the low 8 registers.
-    static const ARMRegisters::RegisterID dataTempRegister = ARMRegisters::ip;
+    static const RegisterID dataTempRegister = ARMRegisters::ip;
     static const RegisterID addressTempRegister = ARMRegisters::r3;
-    static const FPRegisterID fpTempRegister = ARMRegisters::d7;
-
+
+    static const ARMRegisters::FPDoubleRegisterID fpTempRegister = ARMRegisters::d7;
+    inline ARMRegisters::FPSingleRegisterID fpTempRegisterAsSingle() { return ARMRegisters::asSingle(fpTempRegister); }
+
+public:
     struct ArmAddress {
         enum AddressType {
@@ -74 +77 @@
     
 public:
+    typedef ARMRegisters::FPDoubleRegisterID FPRegisterID;
 
     static const Scale ScalePtr = TimesFour;
@@ -223 +227 @@
     }
 
+    void neg32(RegisterID srcDest)
+    {
+        m_assembler.neg(srcDest, srcDest);
+    }
+
     void not32(RegisterID srcDest)
     {
@@ -541 +550 @@
     }
 
+    void loadDouble(const void* address, FPRegisterID dest)
+    {
+        move(ImmPtr(address), addressTempRegister);
+        m_assembler.vldr(dest, addressTempRegister, 0);
+    }
+
     void storeDouble(FPRegisterID src, ImplicitAddress address)
     {
@@ -567 +582 @@
     }
 
+    void divDouble(FPRegisterID src, FPRegisterID dest)
+    {
+        m_assembler.vdiv_F64(dest, dest, src);
+    }
+
     void subDouble(FPRegisterID src, FPRegisterID dest)
     {
@@ -596 +616 @@
     void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
     {
-        m_assembler.vmov(fpTempRegister, src);
-        m_assembler.vcvt_F64_S32(dest, fpTempRegister);
+        m_assembler.vmov(fpTempRegisterAsSingle(), src);
+        m_assembler.vcvt_F64_S32(dest, fpTempRegisterAsSingle());
+    }
+
+    void convertInt32ToDouble(Address address, FPRegisterID dest)
+    {
+        // Fixme: load directly into the fpr!
+        load32(address, dataTempRegister);
+        m_assembler.vmov(fpTempRegisterAsSingle(), dataTempRegister);
+        m_assembler.vcvt_F64_S32(dest, fpTempRegisterAsSingle());
+    }
+
+    void convertInt32ToDouble(AbsoluteAddress address, FPRegisterID dest)
+    {
+        // Fixme: load directly into the fpr!
+        load32(address.m_ptr, dataTempRegister);
+        m_assembler.vmov(fpTempRegisterAsSingle(), dataTempRegister);
+        m_assembler.vcvt_F64_S32(dest, fpTempRegisterAsSingle());
     }
 
@@ -630 +666 @@
     }
 
+    // Convert 'src' to an integer, and places the resulting 'dest'.
+    // If the result is not representable as a 32 bit value, branch.
+    // May also branch for some values that are representable in 32 bits
+    // (specifically, in this case, 0).
+    void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID)
+    {
+        m_assembler.vcvtr_S32_F64(fpTempRegisterAsSingle(), src);
+        m_assembler.vmov(dest, fpTempRegisterAsSingle());
+
+        // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
+        m_assembler.vcvt_F64_S32(fpTempRegister, fpTempRegisterAsSingle());
+        failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, fpTempRegister));
+
+        // If the result is zero, it might have been -0.0, and the double comparison won't catch this!
+        failureCases.append(branchTest32(Zero, dest));
+    }
+
+    void zeroDouble(FPRegisterID dest)
+    {
+        m_assembler.vmov_F64_0(dest);
+    }
 
     // Stack manipulation operations:
@@ -971 +1028 @@
     }
 
+    Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
+    {
+        ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
+        m_assembler.orr_S(dest, dest, src);
+        return Jump(makeBranch(cond));
+    }
+
     Jump branchSub32(Condition cond, RegisterID src, RegisterID dest)
     {
@@ -1035 +1099 @@
     }
 
+    void set32(Condition cond, Address left, RegisterID right, RegisterID dest)
+    {
+        load32(left, dataTempRegister);
+        set32(cond, dataTempRegister, right, dest);
+    }
+
     void set32(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
     {
@@ -1041 +1111 @@
         m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(1));
         m_assembler.mov(dest, ARMThumbImmediate::makeUInt16(0));
+    }
+
+    void set8(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
+    {
+        set32(cond, left, right, dest);
+    }
+
+    void set8(Condition cond, Address left, RegisterID right, RegisterID dest)
+    {
+        set32(cond, left, right, dest);
+    }
+
+    void set8(Condition cond, RegisterID left, Imm32 right, RegisterID dest)
+    {
+        set32(cond, left, right, dest);
     }