Changeset 65303 in webkit for trunk/JavaScriptCore/assembler/MacroAssemblerARM.h

Timestamp:

Aug 12, 2010, 11:49:16 PM (15 years ago)

Author:

[email protected]

Message:

Refactoring the fpu code generator for the ARM port
​https://bugs.webkit.org/show_bug.cgi?id=43842

Reviewed by Gavin Barraclough.

Support up to 32 double precision registers, and the
recent VFP instruction formats. This patch is mainly
a style change which keeps the current functionality.

• assembler/ARMAssembler.h:

(JSC::ARMRegisters::):
(JSC::ARMAssembler::):
(JSC::ARMAssembler::emitInst):
(JSC::ARMAssembler::emitDoublePrecisionInst):
(JSC::ARMAssembler::emitSinglePrecisionInst):
(JSC::ARMAssembler::vadd_f64_r):
(JSC::ARMAssembler::vdiv_f64_r):
(JSC::ARMAssembler::vsub_f64_r):
(JSC::ARMAssembler::vmul_f64_r):
(JSC::ARMAssembler::vcmp_f64_r):
(JSC::ARMAssembler::vsqrt_f64_r):
(JSC::ARMAssembler::vmov_vfp_r):
(JSC::ARMAssembler::vmov_arm_r):
(JSC::ARMAssembler::vcvt_f64_s32_r):
(JSC::ARMAssembler::vcvt_s32_f64_r):
(JSC::ARMAssembler::vmrs_apsr):

• assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::addDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::subDouble):
(JSC::MacroAssemblerARM::mulDouble):
(JSC::MacroAssemblerARM::sqrtDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::branchDouble):
(JSC::MacroAssemblerARM::branchConvertDoubleToInt32):

File:

• trunk/JavaScriptCore/assembler/MacroAssemblerARM.h (modified) (7 diffs)

trunk/JavaScriptCore/assembler/MacroAssemblerARM.h

@@ -796 +796 @@
     void addDouble(FPRegisterID src, FPRegisterID dest)
     {
-        m_assembler.faddd_r(dest, dest, src);
+        m_assembler.vadd_f64_r(dest, dest, src);
     }
 
@@ -807 +807 @@
     void divDouble(FPRegisterID src, FPRegisterID dest)
     {
-        m_assembler.fdivd_r(dest, dest, src);
+        m_assembler.vdiv_f64_r(dest, dest, src);
     }
 
@@ -819 +819 @@
     void subDouble(FPRegisterID src, FPRegisterID dest)
     {
-        m_assembler.fsubd_r(dest, dest, src);
+        m_assembler.vsub_f64_r(dest, dest, src);
     }
 
@@ -830 +830 @@
     void mulDouble(FPRegisterID src, FPRegisterID dest)
     {
-        m_assembler.fmuld_r(dest, dest, src);
+        m_assembler.vmul_f64_r(dest, dest, src);
     }
 
@@ -841 +841 @@
     void sqrtDouble(FPRegisterID src, FPRegisterID dest)
     {
-        m_assembler.fsqrtd_r(dest, src);
+        m_assembler.vsqrt_f64_r(dest, src);
     }
 
     void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
     {
-        m_assembler.fmsr_r(dest, src);
-        m_assembler.fsitod_r(dest, dest);
+        m_assembler.vmov_vfp_r(dest << 1, src);
+        m_assembler.vcvt_f64_s32_r(dest, dest << 1);
     }
 
@@ -869 +869 @@
     Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
     {
-        m_assembler.fcmpd_r(left, right);
-        m_assembler.fmstat();
+        m_assembler.vcmp_f64_r(left, right);
+        m_assembler.vmrs_apsr();
         if (cond & DoubleConditionBitSpecial)
             m_assembler.cmp_r(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::VS);
@@ -894 +894 @@
     void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
     {
-        m_assembler.ftosid_r(ARMRegisters::SD0, src);
-        m_assembler.fmrs_r(dest, ARMRegisters::SD0);
+        m_assembler.vcvt_s32_f64_r(ARMRegisters::SD0 << 1, src);
+        m_assembler.vmov_arm_r(dest, ARMRegisters::SD0 << 1);
 
         // Convert the integer result back to float & compare to the original value - if not equal or unordered (NaN) then jump.
-        m_assembler.fsitod_r(ARMRegisters::SD0, ARMRegisters::SD0);
+        m_assembler.vcvt_f64_s32_r(ARMRegisters::SD0, ARMRegisters::SD0 << 1);
         failureCases.append(branchDouble(DoubleNotEqualOrUnordered, src, ARMRegisters::SD0));