Changeset 65993 in webkit for trunk/JavaScriptCore/assembler/ARMAssembler.h

Timestamp:

Aug 25, 2010, 12:52:16 AM (15 years ago)

Author:

[email protected]

Message:

Enable truncated floating point feature on ARM
​https://bugs.webkit.org/show_bug.cgi?id=44233

Reviewed by Gavin Barraclough.

Enable truncated floating point feature with the help of VCVTR.S32.F64
instruction. If VCVTR.S32.F64 can't fit the result into a 32-bit
integer/register, it saturates at INT_MAX or INT_MIN. Testing this
looks quicker than testing FPSCR for exception.

Inspired by Jacob Bramley's patch from JaegerMonkey

• assembler/ARMAssembler.h:

(JSC::ARMAssembler::):
(JSC::ARMAssembler::cmn_r):
(JSC::ARMAssembler::vcvtr_s32_f64_r):

• assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::supportsFloatingPointTruncate):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):

File:

• trunk/JavaScriptCore/assembler/ARMAssembler.h (modified) (3 diffs)

trunk/JavaScriptCore/assembler/ARMAssembler.h

@@ -162 +162 @@
             VCVT_F64_S32 = 0x0eb80bc0,
             VCVT_S32_F64 = 0x0ebd0b40,
+            VCVTR_S32_F64 = 0x0ebd0bc0,
             VMRS_APSR = 0x0ef1fa10,
 #if WTF_ARM_ARCH_AT_LEAST(5)
@@ -372 +373 @@
         }
 
+        void cmn_r(int rn, ARMWord op2, Condition cc = AL)
+        {
+            emitInst(static_cast<ARMWord>(cc) | CMN | SET_CC, 0, rn, op2);
+        }
+
         void orr_r(int rd, int rn, ARMWord op2, Condition cc = AL)
         {
@@ -577 +583 @@
             ASSERT(!(sd & 0x1)); // sd must be divisible by 2
             emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VCVT_S32_F64, (sd >> 1), 0, dm);
+        }
+
+        void vcvtr_s32_f64_r(int sd, int dm, Condition cc = AL)
+        {
+            ASSERT(!(sd & 0x1)); // sd must be divisible by 2
+            emitDoublePrecisionInst(static_cast<ARMWord>(cc) | VCVTR_S32_F64, (sd >> 1), 0, dm);
         }