Ignore:
Timestamp:
Apr 20, 2011, 11:44:35 AM (14 years ago)
Author:
[email protected]
Message:

Rationalize MacroAssembler branch methods
​https://bugs.webkit.org/show_bug.cgi?id=58950

Reviewed by Oliver Hunt.

The MacroAssembler currently exposes x86's weird behaviour that the 'setcc'
instruction only sets the low 8 bits of a register. Stop that.

Having done so, to clarify remove the 'set32' prefix from test & compare
instructions - these methods all now set a full 32/64 bit register (Ptr size).
The size in the function name should indicate the amount of data being compared.

Also split out the 'Condition' enum into 'RelationalCondition' and
'ResultCondition'. The former is used in binary comparison, the latter is a unary
condition check on the result of an operation.

  • JavaScriptCore.xcodeproj/project.pbxproj:
  • assembler/MacroAssembler.h:

(JSC::MacroAssembler::branchPtr):
(JSC::MacroAssembler::branch32):
(JSC::MacroAssembler::branch16):
(JSC::MacroAssembler::branchTestPtr):
(JSC::MacroAssembler::comparePtr):
(JSC::MacroAssembler::branchAddPtr):
(JSC::MacroAssembler::branchSubPtr):
(JSC::MacroAssembler::branchTest8):

  • assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::branch8):
(JSC::MacroAssemblerARM::branch32):
(JSC::MacroAssemblerARM::branch32WithUnalignedHalfWords):
(JSC::MacroAssemblerARM::branch16):
(JSC::MacroAssemblerARM::branchTest8):
(JSC::MacroAssemblerARM::branchTest32):
(JSC::MacroAssemblerARM::branchAdd32):
(JSC::MacroAssemblerARM::branchMul32):
(JSC::MacroAssemblerARM::branchSub32):
(JSC::MacroAssemblerARM::branchNeg32):
(JSC::MacroAssemblerARM::branchOr32):
(JSC::MacroAssemblerARM::compare32):
(JSC::MacroAssemblerARM::test32):
(JSC::MacroAssemblerARM::test8):
(JSC::MacroAssemblerARM::branchPtrWithPatch):
(JSC::MacroAssemblerARM::ARMCondition):

  • assembler/MacroAssemblerARMv7.h:

(JSC::MacroAssemblerARMv7::branch32):
(JSC::MacroAssemblerARMv7::branch32WithUnalignedHalfWords):
(JSC::MacroAssemblerARMv7::branch16):
(JSC::MacroAssemblerARMv7::branch8):
(JSC::MacroAssemblerARMv7::branchTest32):
(JSC::MacroAssemblerARMv7::branchTest8):
(JSC::MacroAssemblerARMv7::branchAdd32):
(JSC::MacroAssemblerARMv7::branchMul32):
(JSC::MacroAssemblerARMv7::branchOr32):
(JSC::MacroAssemblerARMv7::branchSub32):
(JSC::MacroAssemblerARMv7::compare32):
(JSC::MacroAssemblerARMv7::test32):
(JSC::MacroAssemblerARMv7::test8):
(JSC::MacroAssemblerARMv7::branchPtrWithPatch):
(JSC::MacroAssemblerARMv7::makeBranch):
(JSC::MacroAssemblerARMv7::armV7Condition):

  • assembler/MacroAssemblerMIPS.h:

(JSC::MacroAssemblerMIPS::branch8):
(JSC::MacroAssemblerMIPS::branch32):
(JSC::MacroAssemblerMIPS::branch32WithUnalignedHalfWords):
(JSC::MacroAssemblerMIPS::branch16):
(JSC::MacroAssemblerMIPS::branchTest32):
(JSC::MacroAssemblerMIPS::branchTest8):
(JSC::MacroAssemblerMIPS::branchAdd32):
(JSC::MacroAssemblerMIPS::branchMul32):
(JSC::MacroAssemblerMIPS::branchSub32):
(JSC::MacroAssemblerMIPS::branchOr32):
(JSC::MacroAssemblerMIPS::compare32):
(JSC::MacroAssemblerMIPS::test8):
(JSC::MacroAssemblerMIPS::test32):
(JSC::MacroAssemblerMIPS::branchPtrWithPatch):

  • assembler/MacroAssemblerX86.h:

(JSC::MacroAssemblerX86::branch32):
(JSC::MacroAssemblerX86::branchPtrWithPatch):

  • assembler/MacroAssemblerX86Common.h:

(JSC::MacroAssemblerX86Common::branch8):
(JSC::MacroAssemblerX86Common::branch32):
(JSC::MacroAssemblerX86Common::branch32WithUnalignedHalfWords):
(JSC::MacroAssemblerX86Common::branch16):
(JSC::MacroAssemblerX86Common::branchTest32):
(JSC::MacroAssemblerX86Common::branchTest8):
(JSC::MacroAssemblerX86Common::branchAdd32):
(JSC::MacroAssemblerX86Common::branchMul32):
(JSC::MacroAssemblerX86Common::branchSub32):
(JSC::MacroAssemblerX86Common::branchNeg32):
(JSC::MacroAssemblerX86Common::branchOr32):
(JSC::MacroAssemblerX86Common::compare32):
(JSC::MacroAssemblerX86Common::test8):
(JSC::MacroAssemblerX86Common::test32):
(JSC::MacroAssemblerX86Common::x86Condition):

  • assembler/MacroAssemblerX86_64.h:

(JSC::MacroAssemblerX86_64::comparePtr):
(JSC::MacroAssemblerX86_64::branchPtr):
(JSC::MacroAssemblerX86_64::branchTestPtr):
(JSC::MacroAssemblerX86_64::branchAddPtr):
(JSC::MacroAssemblerX86_64::branchSubPtr):
(JSC::MacroAssemblerX86_64::branchPtrWithPatch):
(JSC::MacroAssemblerX86_64::branchTest8):

  • dfg/DFGSpeculativeJIT.cpp:

(JSC::DFG::SpeculativeJIT::compile):

  • jit/JITOpcodes.cpp:

(JSC::JIT::emit_op_eq):
(JSC::JIT::emit_op_neq):
(JSC::JIT::compileOpStrictEq):
(JSC::JIT::emit_op_eq_null):
(JSC::JIT::emit_op_neq_null):

  • jit/JITOpcodes32_64.cpp:

(JSC::JIT::emit_op_eq):
(JSC::JIT::emit_op_neq):
(JSC::JIT::compileOpStrictEq):
(JSC::JIT::emit_op_eq_null):
(JSC::JIT::emit_op_neq_null):

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/assembler/MacroAssemblerMIPS.h

    r82130 r84399  
    5858    static const FPRegisterID fpTempRegister = MIPSRegisters::f16;
    5959
    60     enum Condition {
     60    enum RelationalCondition {
    6161        Equal,
    6262        NotEqual,
    … …  
    6868        GreaterThanOrEqual,
    6969        LessThan,
    70         LessThanOrEqual,
     70        LessThanOrEqual
     71    };
     72
     73    enum ResultCondition {
    7174        Overflow,
    7275        Signed,
    … …  
    901904    // an optional second operand of a mask under which to perform the test.
    902905
    903     Jump branch8(Condition cond, Address left, TrustedImm32 right)
     906    Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
    904907    {
    905908        // Make sure the immediate value is unsigned 8 bits.
    … …  
    910913    }
    911914
    912     Jump branch32(Condition cond, RegisterID left, RegisterID right)
     915    Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right)
    913916    {
    914917        if (cond == Equal || cond == Zero)
    … …  
    986989    }
    987990
    988     Jump branch32(Condition cond, RegisterID left, TrustedImm32 right)
     991    Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right)
    989992    {
    990993        move(right, immTempRegister);
    … …  
    992995    }
    993996
    994     Jump branch32(Condition cond, RegisterID left, Address right)
     997    Jump branch32(RelationalCondition cond, RegisterID left, Address right)
    995998    {
    996999        load32(right, dataTempRegister);
    … …  
    9981001    }
    9991002
    1000     Jump branch32(Condition cond, Address left, RegisterID right)
     1003    Jump branch32(RelationalCondition cond, Address left, RegisterID right)
    10011004    {
    10021005        load32(left, dataTempRegister);
    … …  
    10041007    }
    10051008
    1006     Jump branch32(Condition cond, Address left, TrustedImm32 right)
     1009    Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)
    10071010    {
    10081011        load32(left, dataTempRegister);
    … …  
    10111014    }
    10121015
    1013     Jump branch32(Condition cond, BaseIndex left, TrustedImm32 right)
     1016    Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
    10141017    {
    10151018        load32(left, dataTempRegister);
    … …  
    10201023    }
    10211024
    1022     Jump branch32WithUnalignedHalfWords(Condition cond, BaseIndex left, TrustedImm32 right)
     1025    Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
    10231026    {
    10241027        load32WithUnalignedHalfWords(left, dataTempRegister);
    … …  
    10301033    }
    10311034
    1032     Jump branch32(Condition cond, AbsoluteAddress left, RegisterID right)
     1035    Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
    10331036    {
    10341037        load32(left.m_ptr, dataTempRegister);
    … …  
    10361039    }
    10371040
    1038     Jump branch32(Condition cond, AbsoluteAddress left, TrustedImm32 right)
     1041    Jump branch32(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
    10391042    {
    10401043        load32(left.m_ptr, dataTempRegister);
    … …  
    10431046    }
    10441047
    1045     Jump branch16(Condition cond, BaseIndex left, RegisterID right)
     1048    Jump branch16(RelationalCondition cond, BaseIndex left, RegisterID right)
    10461049    {
    10471050        load16(left, dataTempRegister);
    … …  
    10491052    }
    10501053
    1051     Jump branch16(Condition cond, BaseIndex left, TrustedImm32 right)
     1054    Jump branch16(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
    10521055    {
    10531056        ASSERT(!(right.m_value & 0xFFFF0000));
    … …  
    10591062    }
    10601063
    1061     Jump branchTest32(Condition cond, RegisterID reg, RegisterID mask)
     1064    Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
    10621065    {
    10631066        ASSERT((cond == Zero) || (cond == NonZero));
    … …  
    10681071    }
    10691072
    1070     Jump branchTest32(Condition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
     1073    Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
    10711074    {
    10721075        ASSERT((cond == Zero) || (cond == NonZero));
    … …  
    10801083    }
    10811084
    1082     Jump branchTest32(Condition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
     1085    Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
    10831086    {
    10841087        load32(address, dataTempRegister);
    … …  
    10861089    }
    10871090
    1088     Jump branchTest32(Condition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
     1091    Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
    10891092    {
    10901093        load32(address, dataTempRegister);
    … …  
    10921095    }
    10931096
    1094     Jump branchTest8(Condition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
     1097    Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
    10951098    {
    10961099        load8(address, dataTempRegister);
    … …  
    11281131    //   operation caused an overflow to occur.
    11291132
    1130     Jump branchAdd32(Condition cond, RegisterID src, RegisterID dest)
     1133    Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
    11311134    {
    11321135        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
    … …  
    11751178    }
    11761179
    1177     Jump branchAdd32(Condition cond, TrustedImm32 imm, RegisterID dest)
     1180    Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
    11781181    {
    11791182        move(imm, immTempRegister);
    … …  
    11811184    }
    11821185
    1183     Jump branchMul32(Condition cond, RegisterID src, RegisterID dest)
     1186    Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
    11841187    {
    11851188        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
    … …  
    12261229    }
    12271230
    1228     Jump branchMul32(Condition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)
     1231    Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)
    12291232    {
    12301233        move(imm, immTempRegister);
    … …  
    12331236    }
    12341237
    1235     Jump branchSub32(Condition cond, RegisterID src, RegisterID dest)
     1238    Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
    12361239    {
    12371240        ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
    … …  
    12801283    }
    12811284
    1282     Jump branchSub32(Condition cond, TrustedImm32 imm, RegisterID dest)
     1285    Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
    12831286    {
    12841287        move(imm, immTempRegister);
    … …  
    12861289    }
    12871290
    1288     Jump branchOr32(Condition cond, RegisterID src, RegisterID dest)
     1291    Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
    12891292    {
    12901293        ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
    … …  
    13561359    }
    13571360
    1358     void set8Compare32(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
    1359     {
    1360         set32Compare32(cond, left, right, dest);
    1361     }
    1362 
    1363     void set8Compare32(Condition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
    1364     {
    1365         move(right, immTempRegister);
    1366         set32Compare32(cond, left, immTempRegister, dest);
    1367     }
    1368 
    1369     void set32Compare32(Condition cond, RegisterID left, RegisterID right, RegisterID dest)
     1361    void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
    13701362    {
    13711363        if (cond == Equal || cond == Zero) {
    … …  
    14181410    }
    14191411
    1420     void set32Compare32(Condition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
     1412    void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
    14211413    {
    14221414        move(right, immTempRegister);
    1423         set32Compare32(cond, left, immTempRegister, dest);
    1424     }
    1425 
    1426     void set32Test8(Condition cond, Address address, TrustedImm32 mask, RegisterID dest)
     1415        compare32(cond, left, immTempRegister, dest);
     1416    }
     1417
     1418    void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
    14271419    {
    14281420        ASSERT((cond == Zero) || (cond == NonZero));
    … …  
    14441436    }
    14451437
    1446     void set32Test32(Condition cond, Address address, TrustedImm32 mask, RegisterID dest)
     1438    void test32(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
    14471439    {
    14481440        ASSERT((cond == Zero) || (cond == NonZero));
    … …  
    14821474    }
    14831475
    1484     Jump branchPtrWithPatch(Condition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
     1476    Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
    14851477    {
    14861478        m_fixedWidth = true;
    … …  
    14911483    }
    14921484
    1493     Jump branchPtrWithPatch(Condition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
     1485    Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
    14941486    {
    14951487        m_fixedWidth = true;
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