Changeset 86699 in webkit for trunk/Source/JavaScriptCore/assembler/X86Assembler.h

Timestamp:

May 17, 2011, 1:02:41 PM (14 years ago)

Author:

[email protected]

Message:

2011-05-16 Oliver Hunt <​[email protected]>

Reviewed by Gavin Barraclough.

Reduce code size for inline cache
​https://bugs.webkit.org/show_bug.cgi?id=60942

This patch introduces the concept of a "compact" address that
allows individual architectures to control the maximum offset
used for the inline path of get_by_id. This reduces the code
size of get_by_id by 3 bytes on x86 and x86_64 and slightly
improves performance on v8 tests.

• assembler/ARMAssembler.h: (JSC::ARMAssembler::repatchCompact):
• assembler/ARMv7Assembler.h: (JSC::ARMv7Assembler::repatchCompact):
• assembler/AbstractMacroAssembler.h: (JSC::AbstractMacroAssembler::DataLabelCompact::DataLabelCompact): (JSC::AbstractMacroAssembler::differenceBetween): (JSC::AbstractMacroAssembler::repatchCompact):
• assembler/CodeLocation.h: (JSC::CodeLocationDataLabelCompact::CodeLocationDataLabelCompact): (JSC::CodeLocationCommon::dataLabelCompactAtOffset):
• assembler/LinkBuffer.h: (JSC::LinkBuffer::locationOf):
• assembler/MIPSAssembler.h: (JSC::MIPSAssembler::repatchCompact):
• assembler/MacroAssembler.h: (JSC::MacroAssembler::loadPtrWithCompactAddressOffsetPatch):
• assembler/MacroAssemblerARM.h: (JSC::MacroAssemblerARM::load32WithCompactAddressOffsetPatch):
• assembler/MacroAssemblerARMv7.h: (JSC::MacroAssemblerARMv7::load32WithCompactAddressOffsetPatch):
• assembler/MacroAssemblerMIPS.h: (JSC::MacroAssemblerMIPS::load32WithCompactAddressOffsetPatch):
• assembler/MacroAssemblerSH4.h: (JSC::MacroAssemblerSH4::load32WithAddressOffsetPatch):
• assembler/MacroAssemblerX86.h: (JSC::MacroAssemblerX86::repatchCompact):
• assembler/MacroAssemblerX86Common.h: (JSC::MacroAssemblerX86Common::loadCompactWithAddressOffsetPatch):
• assembler/MacroAssemblerX86_64.h: (JSC::MacroAssemblerX86_64::loadPtrWithCompactAddressOffsetPatch):
• assembler/RepatchBuffer.h: (JSC::RepatchBuffer::repatch):
• assembler/SH4Assembler.h: (JSC::SH4Assembler::repatchCompact):
• assembler/X86Assembler.h: (JSC::X86Assembler::movl_mr_disp8): (JSC::X86Assembler::movq_mr_disp8): (JSC::X86Assembler::repatchCompact): (JSC::X86Assembler::setInt8): (JSC::X86Assembler::X86InstructionFormatter::oneByteOp_disp8): (JSC::X86Assembler::X86InstructionFormatter::oneByteOp64_disp8): (JSC::X86Assembler::X86InstructionFormatter::memoryModRM):
• jit/JIT.h:
• jit/JITPropertyAccess.cpp: (JSC::JIT::compileGetByIdHotPath): (JSC::JIT::emit_op_put_by_id): (JSC::JIT::patchGetByIdSelf):
• jit/JITPropertyAccess32_64.cpp: (JSC::JIT::compileGetByIdHotPath): (JSC::JIT::emit_op_put_by_id): (JSC::JIT::patchGetByIdSelf):
• jit/JITStubs.cpp: (JSC::JITThunks::tryCacheGetByID):

File:

• trunk/Source/JavaScriptCore/assembler/X86Assembler.h (modified) (7 diffs)

trunk/Source/JavaScriptCore/assembler/X86Assembler.h

@@ -1020 +1020 @@
         m_formatter.oneByteOp_disp32(OP_MOV_GvEv, dst, base, offset);
     }
+    
+    void movl_mr_disp8(int offset, RegisterID base, RegisterID dst)
+    {
+        m_formatter.oneByteOp_disp8(OP_MOV_GvEv, dst, base, offset);
+    }
 
     void movl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
@@ -1089 +1094 @@
     {
         m_formatter.oneByteOp64_disp32(OP_MOV_GvEv, dst, base, offset);
+    }
+
+    void movq_mr_disp8(int offset, RegisterID base, RegisterID dst)
+    {
+        m_formatter.oneByteOp64_disp8(OP_MOV_GvEv, dst, base, offset);
     }
 
@@ -1538 +1548 @@
         setRel32(from, to);
     }
+    
+    static void repatchCompact(void* where, int32_t value)
+    {
+        ASSERT(value >= 0);
+        ASSERT(value <= std::numeric_limits<int8_t>::max());
+        setInt8(where, value);
+    }
 
     static void repatchInt32(void* where, int32_t value)
@@ -1587 +1604 @@
     {
         reinterpret_cast<int32_t*>(where)[-1] = value;
+    }
+    
+    static void setInt8(void* where, int8_t value)
+    {
+        reinterpret_cast<int8_t*>(where)[-1] = value;
     }
 
@@ -1662 +1684 @@
             memoryModRM_disp32(reg, base, offset);
         }
+        
+        void oneByteOp_disp8(OneByteOpcodeID opcode, int reg, RegisterID base, int offset)
+        {
+            m_buffer.ensureSpace(maxInstructionSize);
+            emitRexIfNeeded(reg, 0, base);
+            m_buffer.putByteUnchecked(opcode);
+            memoryModRM_disp8(reg, base, offset);
+        }
 
         void oneByteOp(OneByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset)
@@ -1767 +1797 @@
             m_buffer.putByteUnchecked(opcode);
             memoryModRM_disp32(reg, base, offset);
+        }
+        
+        void oneByteOp64_disp8(OneByteOpcodeID opcode, int reg, RegisterID base, int offset)
+        {
+            m_buffer.ensureSpace(maxInstructionSize);
+            emitRexW(reg, 0, base);
+            m_buffer.putByteUnchecked(opcode);
+            memoryModRM_disp8(reg, base, offset);
         }
 
@@ -2000 +2038 @@
             }
         }
-    
+
+        void memoryModRM_disp8(int reg, RegisterID base, int offset)
+        {
+            // A base of esp or r12 would be interpreted as a sib, so force a sib with no index & put the base in there.
+            ASSERT(CAN_SIGN_EXTEND_8_32(offset));
+#if CPU(X86_64)
+            if ((base == hasSib) || (base == hasSib2)) {
+#else
+            if (base == hasSib) {
+#endif
+                putModRmSib(ModRmMemoryDisp8, reg, base, noIndex, 0);
+                m_buffer.putByteUnchecked(offset);
+            } else {
+                putModRm(ModRmMemoryDisp8, reg, base);
+                m_buffer.putByteUnchecked(offset);
+            }
+        }
+
         void memoryModRM_disp32(int reg, RegisterID base, int offset)
         {