Ignore:
Timestamp:
Jul 5, 2012, 12:04:16 AM (13 years ago)
Author:
[email protected]
Message:

Port DFG JIT to traditional ARM
​https://bugs.webkit.org/show_bug.cgi?id=90198

Reviewed by Filip Pizlo.

Source/JavaScriptCore:

This patch contains the macro assembler part of the
DFG JIT support on ARM systems with fixed 32 bit instruction
width. A large amount of old code was refactored, and the ARMv4
or lower support is removed from the macro assembler.

Sunspider is improved by 8%, and V8 is 92%.

  • assembler/ARMAssembler.cpp:

(JSC::ARMAssembler::dataTransfer32):
(JSC::ARMAssembler::baseIndexTransfer32):
(JSC):
(JSC::ARMAssembler::dataTransfer16):
(JSC::ARMAssembler::baseIndexTransfer16):
(JSC::ARMAssembler::dataTransferFloat):
(JSC::ARMAssembler::baseIndexTransferFloat):
(JSC::ARMAssembler::executableCopy):

  • assembler/ARMAssembler.h:

(JSC::ARMAssembler::ARMAssembler):
(JSC::ARMAssembler::emitInst):
(JSC::ARMAssembler::vmov_f64_r):
(ARMAssembler):
(JSC::ARMAssembler::vabs_f64_r):
(JSC::ARMAssembler::vneg_f64_r):
(JSC::ARMAssembler::ldr_imm):
(JSC::ARMAssembler::ldr_un_imm):
(JSC::ARMAssembler::dtr_u):
(JSC::ARMAssembler::dtr_ur):
(JSC::ARMAssembler::dtr_d):
(JSC::ARMAssembler::dtr_dr):
(JSC::ARMAssembler::dtrh_u):
(JSC::ARMAssembler::dtrh_ur):
(JSC::ARMAssembler::dtrh_d):
(JSC::ARMAssembler::dtrh_dr):
(JSC::ARMAssembler::fdtr_u):
(JSC::ARMAssembler::fdtr_d):
(JSC::ARMAssembler::push_r):
(JSC::ARMAssembler::pop_r):
(JSC::ARMAssembler::poke_r):
(JSC::ARMAssembler::peek_r):
(JSC::ARMAssembler::vmov_vfp64_r):
(JSC::ARMAssembler::vmov_arm64_r):
(JSC::ARMAssembler::vmov_vfp32_r):
(JSC::ARMAssembler::vmov_arm32_r):
(JSC::ARMAssembler::vcvt_u32_f64_r):
(JSC::ARMAssembler::vcvt_f64_f32_r):
(JSC::ARMAssembler::vcvt_f32_f64_r):
(JSC::ARMAssembler::clz_r):
(JSC::ARMAssembler::bkpt):
(JSC::ARMAssembler::bx):
(JSC::ARMAssembler::blx):
(JSC::ARMAssembler::labelIgnoringWatchpoints):
(JSC::ARMAssembler::labelForWatchpoint):
(JSC::ARMAssembler::label):
(JSC::ARMAssembler::getLdrImmAddress):
(JSC::ARMAssembler::replaceWithJump):
(JSC::ARMAssembler::maxJumpReplacementSize):
(JSC::ARMAssembler::getOp2Byte):
(JSC::ARMAssembler::getOp2Half):
(JSC::ARMAssembler::RM):
(JSC::ARMAssembler::RS):
(JSC::ARMAssembler::RD):
(JSC::ARMAssembler::RN):

  • assembler/AssemblerBufferWithConstantPool.h:

(JSC::AssemblerBufferWithConstantPool::ensureSpaceForAnyInstruction):

  • assembler/MacroAssemblerARM.cpp:

(JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):

  • assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::add32):
(MacroAssemblerARM):
(JSC::MacroAssemblerARM::and32):
(JSC::MacroAssemblerARM::lshift32):
(JSC::MacroAssemblerARM::mul32):
(JSC::MacroAssemblerARM::neg32):
(JSC::MacroAssemblerARM::rshift32):
(JSC::MacroAssemblerARM::urshift32):
(JSC::MacroAssemblerARM::xor32):
(JSC::MacroAssemblerARM::load8):
(JSC::MacroAssemblerARM::load8Signed):
(JSC::MacroAssemblerARM::load16):
(JSC::MacroAssemblerARM::load16Signed):
(JSC::MacroAssemblerARM::load32):
(JSC::MacroAssemblerARM::load32WithAddressOffsetPatch):
(JSC::MacroAssemblerARM::store32WithAddressOffsetPatch):
(JSC::MacroAssemblerARM::store8):
(JSC::MacroAssemblerARM::store16):
(JSC::MacroAssemblerARM::store32):
(JSC::MacroAssemblerARM::move):
(JSC::MacroAssemblerARM::jump):
(JSC::MacroAssemblerARM::branchAdd32):
(JSC::MacroAssemblerARM::mull32):
(JSC::MacroAssemblerARM::branchMul32):
(JSC::MacroAssemblerARM::nearCall):
(JSC::MacroAssemblerARM::compare32):
(JSC::MacroAssemblerARM::test32):
(JSC::MacroAssemblerARM::sub32):
(JSC::MacroAssemblerARM::call):
(JSC::MacroAssemblerARM::loadFloat):
(JSC::MacroAssemblerARM::loadDouble):
(JSC::MacroAssemblerARM::storeFloat):
(JSC::MacroAssemblerARM::storeDouble):
(JSC::MacroAssemblerARM::moveDouble):
(JSC::MacroAssemblerARM::addDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::subDouble):
(JSC::MacroAssemblerARM::mulDouble):
(JSC::MacroAssemblerARM::absDouble):
(JSC::MacroAssemblerARM::negateDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::convertFloatToDouble):
(JSC::MacroAssemblerARM::convertDoubleToFloat):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):
(JSC::MacroAssemblerARM::branchTruncateDoubleToUint32):
(JSC::MacroAssemblerARM::truncateDoubleToInt32):
(JSC::MacroAssemblerARM::truncateDoubleToUint32):
(JSC::MacroAssemblerARM::branchConvertDoubleToInt32):
(JSC::MacroAssemblerARM::branchDoubleNonZero):
(JSC::MacroAssemblerARM::branchDoubleZeroOrNaN):
(JSC::MacroAssemblerARM::invert):
(JSC::MacroAssemblerARM::replaceWithJump):
(JSC::MacroAssemblerARM::maxJumpReplacementSize):
(JSC::MacroAssemblerARM::call32):

  • assembler/SH4Assembler.h:

(JSC::SH4Assembler::label):

  • dfg/DFGAssemblyHelpers.h:

(JSC::DFG::AssemblyHelpers::debugCall):
(JSC::DFG::AssemblyHelpers::boxDouble):
(JSC::DFG::AssemblyHelpers::unboxDouble):

  • dfg/DFGCCallHelpers.h:

(CCallHelpers):
(JSC::DFG::CCallHelpers::setupArguments):

  • dfg/DFGFPRInfo.h:

(DFG):

  • dfg/DFGGPRInfo.h:

(DFG):
(GPRInfo):

  • dfg/DFGOperations.cpp:

(JSC):

  • dfg/DFGSpeculativeJIT.h:

(SpeculativeJIT):
(JSC::DFG::SpeculativeJIT::appendCallWithExceptionCheckSetResult):
(JSC::DFG::SpeculativeJIT::appendCallSetResult):

  • jit/JITStubs.cpp:

(JSC):

  • jit/JITStubs.h:

(JITStackFrame):

  • jit/JSInterfaceJIT.h:

(JSInterfaceJIT):

Source/WTF:

Enabling DFG JIT on ARM systems with 32 bit instruction set.

  • wtf/InlineASM.h:
  • wtf/Platform.h:
File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/assembler/ARMAssembler.cpp

    r118413 r121885  
    263263// Memory load/store helpers
    264264
    265 void ARMAssembler::dataTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, int32_t offset, bool bytes)
    266 {
    267     ARMWord transferFlag = bytes ? DT_BYTE : 0;
     265void ARMAssembler::dataTransfer32(DataTransferTypeA transferType, RegisterID srcDst, RegisterID base, int32_t offset)
     266{
    268267    if (offset >= 0) {
    269268        if (offset <= 0xfff)
    270             dtr_u(isLoad, srcDst, base, offset | transferFlag);
     269            dtr_u(transferType, srcDst, base, offset);
    271270        else if (offset <= 0xfffff) {
    272271            add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
    273             dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
     272            dtr_u(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
    274273        } else {
    275274            moveImm(offset, ARMRegisters::S0);
    276             dtr_ur(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
     275            dtr_ur(transferType, srcDst, base, ARMRegisters::S0);
    277276        }
    278277    } else {
    279278        if (offset >= -0xfff)
    280             dtr_d(isLoad, srcDst, base, -offset | transferFlag);
     279            dtr_d(transferType, srcDst, base, -offset);
    281280        else if (offset >= -0xfffff) {
    282281            sub_r(ARMRegisters::S0, base, OP2_IMM | (-offset >> 12) | (10 << 8));
    283             dtr_d(isLoad, srcDst, ARMRegisters::S0, (-offset & 0xfff) | transferFlag);
     282            dtr_d(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
    284283        } else {
    285284            moveImm(offset, ARMRegisters::S0);
    286             dtr_ur(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
    287         }
    288     }
    289 }
    290 
    291 void ARMAssembler::baseIndexTransfer32(bool isLoad, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset, bool bytes)
    292 {
    293     ARMWord op2;
    294     ARMWord transferFlag = bytes ? DT_BYTE : 0;
    295 
     285            dtr_ur(transferType, srcDst, base, ARMRegisters::S0);
     286        }
     287    }
     288}
     289
     290void ARMAssembler::baseIndexTransfer32(DataTransferTypeA transferType, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
     291{
    296292    ASSERT(scale >= 0 && scale <= 3);
    297     op2 = lsl(index, scale);
    298 
    299     if (offset >= 0 && offset <= 0xfff) {
    300         add_r(ARMRegisters::S0, base, op2);
    301         dtr_u(isLoad, srcDst, ARMRegisters::S0, offset | transferFlag);
     293    ARMWord op2 = lsl(index, scale);
     294
     295    if (!offset) {
     296        dtr_ur(transferType, srcDst, base, op2);
    302297        return;
    303298    }
    304     if (offset <= 0 && offset >= -0xfff) {
    305         add_r(ARMRegisters::S0, base, op2);
    306         dtr_d(isLoad, srcDst, ARMRegisters::S0, (-offset & 0xfff) | transferFlag);
     299
     300    add_r(ARMRegisters::S1, base, op2);
     301    dataTransfer32(transferType, srcDst, ARMRegisters::S1, offset);
     302}
     303
     304void ARMAssembler::dataTransfer16(DataTransferTypeB transferType, RegisterID srcDst, RegisterID base, int32_t offset)
     305{
     306    if (offset >= 0) {
     307        if (offset <= 0xff)
     308            dtrh_u(transferType, srcDst, base, getOp2Half(offset));
     309        else if (offset <= 0xffff) {
     310            add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 8) | (12 << 8));
     311            dtrh_u(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
     312        } else {
     313            moveImm(offset, ARMRegisters::S0);
     314            dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);
     315        }
     316    } else {
     317        if (offset >= -0xff)
     318            dtrh_d(transferType, srcDst, base, getOp2Half(-offset));
     319        else if (offset >= -0xffff) {
     320            sub_r(ARMRegisters::S0, base, OP2_IMM | (-offset >> 8) | (12 << 8));
     321            dtrh_d(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
     322        } else {
     323            moveImm(offset, ARMRegisters::S0);
     324            dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);
     325        }
     326    }
     327}
     328
     329void ARMAssembler::baseIndexTransfer16(DataTransferTypeB transferType, RegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
     330{
     331    if (!scale && !offset) {
     332        dtrh_ur(transferType, srcDst, base, index);
    307333        return;
    308334    }
    309335
    310     ldr_un_imm(ARMRegisters::S0, offset);
    311     add_r(ARMRegisters::S0, ARMRegisters::S0, op2);
    312     dtr_ur(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
    313 }
    314 
    315 void ARMAssembler::doubleTransfer(bool isLoad, FPRegisterID srcDst, RegisterID base, int32_t offset)
     336    add_r(ARMRegisters::S1, base, lsl(index, scale));
     337    dataTransfer16(transferType, srcDst, ARMRegisters::S1, offset);
     338}
     339
     340void ARMAssembler::dataTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, int32_t offset)
    316341{
    317342    // VFP cannot directly access memory that is not four-byte-aligned
    318343    if (!(offset & 0x3)) {
    319344        if (offset <= 0x3ff && offset >= 0) {
    320             fdtr_u(isLoad, srcDst, base, offset >> 2);
     345            fdtr_u(transferType, srcDst, base, offset >> 2);
    321346            return;
    322347        }
    323348        if (offset <= 0x3ffff && offset >= 0) {
    324349            add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 10) | (11 << 8));
    325             fdtr_u(isLoad, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
     350            fdtr_u(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    326351            return;
    327352        }
    … …  
    329354
    330355        if (offset <= 0x3ff && offset >= 0) {
    331             fdtr_d(isLoad, srcDst, base, offset >> 2);
     356            fdtr_d(transferType, srcDst, base, offset >> 2);
    332357            return;
    333358        }
    334359        if (offset <= 0x3ffff && offset >= 0) {
    335360            sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 10) | (11 << 8));
    336             fdtr_d(isLoad, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
     361            fdtr_d(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    337362            return;
    338363        }
    … …  
    340365    }
    341366
    342     ldr_un_imm(ARMRegisters::S0, offset);
     367    moveImm(offset, ARMRegisters::S0);
    343368    add_r(ARMRegisters::S0, ARMRegisters::S0, base);
    344     fdtr_u(isLoad, srcDst, ARMRegisters::S0, 0);
     369    fdtr_u(transferType, srcDst, ARMRegisters::S0, 0);
     370}
     371
     372void ARMAssembler::baseIndexTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
     373{
     374    add_r(ARMRegisters::S1, base, lsl(index, scale));
     375    dataTransferFloat(transferType, srcDst, ARMRegisters::S1, offset);
    345376}
    346377
    … …  
    362393        if (*addr != InvalidBranchTarget) {
    363394            if (!(iter->m_offset & 1)) {
    364                 int diff = reinterpret_cast_ptr<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching);
    365 
    366                 if ((diff <= BOFFSET_MAX && diff >= BOFFSET_MIN)) {
    367                     *ldrAddr = B | getConditionalField(*ldrAddr) | (diff & BRANCH_MASK);
     395                intptr_t difference = reinterpret_cast_ptr<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching);
     396
     397                if ((difference <= BOFFSET_MAX && difference >= BOFFSET_MIN)) {
     398                    *ldrAddr = B | getConditionalField(*ldrAddr) | (difference & BRANCH_MASK);
    368399                    continue;
    369400                }
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