Ignore:
Timestamp:
Aug 7, 2012, 3:55:04 PM (13 years ago)
Author:
[email protected]
Message:

Refactor magic numbers in the ARM port of DFG-JIT
​https://bugs.webkit.org/show_bug.cgi?id=93348

Patch by Gabor Ballabas <​[email protected]> on 2012-08-07
Reviewed by Eric Seidel.

Introduce new names for hard-coded magic numbers.
Refactor constant with confusing names to more descriptive ones.

  • assembler/ARMAssembler.cpp:

(JSC::ARMAssembler::patchConstantPoolLoad):
(JSC::ARMAssembler::getOp2):
(JSC::ARMAssembler::genInt):
(JSC::ARMAssembler::getImm):
(JSC::ARMAssembler::moveImm):
(JSC::ARMAssembler::encodeComplexImm):
(JSC::ARMAssembler::dataTransfer32):
(JSC::ARMAssembler::dataTransfer16):
(JSC::ARMAssembler::dataTransferFloat):
(JSC::ARMAssembler::executableCopy):

  • assembler/ARMAssembler.h:

(JSC::ARMAssembler::emitInstruction):
(JSC::ARMAssembler::ands_r):
(JSC::ARMAssembler::eors_r):
(JSC::ARMAssembler::subs_r):
(JSC::ARMAssembler::rsbs_r):
(JSC::ARMAssembler::adds_r):
(JSC::ARMAssembler::adcs_r):
(JSC::ARMAssembler::sbcs_r):
(JSC::ARMAssembler::rscs_r):
(JSC::ARMAssembler::tst_r):
(JSC::ARMAssembler::teq_r):
(JSC::ARMAssembler::cmp_r):
(JSC::ARMAssembler::cmn_r):
(JSC::ARMAssembler::orrs_r):
(JSC::ARMAssembler::movs_r):
(JSC::ARMAssembler::bics_r):
(JSC::ARMAssembler::mvns_r):
(JSC::ARMAssembler::muls_r):
(JSC::ARMAssembler::ldr_imm):
(JSC::ARMAssembler::ldr_un_imm):
(JSC::ARMAssembler::dtr_u):
(JSC::ARMAssembler::dtr_ur):
(JSC::ARMAssembler::dtr_dr):
(JSC::ARMAssembler::dtrh_u):
(JSC::ARMAssembler::dtrh_ur):
(JSC::ARMAssembler::fdtr_u):
(JSC::ARMAssembler::push_r):
(JSC::ARMAssembler::pop_r):
(JSC::ARMAssembler::getLdrImmAddress):
(JSC::ARMAssembler::getLdrImmAddressOnPool):
(JSC::ARMAssembler::patchConstantPoolLoad):
(JSC::ARMAssembler::repatchCompact):
(JSC::ARMAssembler::replaceWithJump):
(JSC::ARMAssembler::replaceWithLoad):
(JSC::ARMAssembler::replaceWithAddressComputation):
(JSC::ARMAssembler::getOp2Byte):
(JSC::ARMAssembler::getOp2Half):
(JSC::ARMAssembler::getImm16Op2):
(JSC::ARMAssembler::placeConstantPoolBarrier):
(JSC::ARMAssembler::getConditionalField):

  • assembler/MacroAssemblerARM.cpp:

(JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):

  • assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::and32):
(JSC::MacroAssemblerARM::branch32):
(JSC::MacroAssemblerARM::branchTest32):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/assembler/ARMAssembler.cpp

    r121885 r124930  
    4747        *ldr = (*ldr & ~0xfff) | diff;
    4848    } else
    49         *ldr = (*ldr & ~(0xfff | ARMAssembler::DT_UP)) | sizeof(ARMWord);
     49        *ldr = (*ldr & ~(0xfff | ARMAssembler::DataTransferUp)) | sizeof(ARMWord);
    5050}
    5151
    … …  
    5757
    5858    if (imm <= 0xff)
    59         return OP2_IMM | imm;
     59        return Op2Immediate | imm;
    6060
    6161    if ((imm & 0xff000000) == 0) {
    … …  
    8484
    8585    if ((imm & 0x00ffffff) == 0)
    86         return OP2_IMM | (imm >> 24) | (rol << 8);
    87 
    88     return INVALID_IMM;
     86        return Op2Immediate | (imm >> 24) | (rol << 8);
     87
     88    return InvalidImmediate;
    8989}
    9090
    … …  
    130130
    131131    if ((imm & 0xff000000) == 0) {
    132         imm1 = OP2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8);
    133         imm2 = OP2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8);
     132        imm1 = Op2Immediate | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8);
     133        imm2 = Op2Immediate | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8);
    134134    } else if (imm & 0xc0000000) {
    135         imm1 = OP2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
     135        imm1 = Op2Immediate | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
    136136        imm <<= 8;
    137137        rol += 4;
    … …  
    153153
    154154        if ((imm & 0x00ffffff) == 0)
    155             imm2 = OP2_IMM | (imm >> 24) | ((rol & 0xf) << 8);
     155            imm2 = Op2Immediate | (imm >> 24) | ((rol & 0xf) << 8);
    156156        else
    157157            return 0;
    … …  
    167167        }
    168168
    169         imm1 = OP2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
     169        imm1 = Op2Immediate | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
    170170        imm <<= 8;
    171171        rol += 4;
    … …  
    182182
    183183        if ((imm & 0x00ffffff) == 0)
    184             imm2 = OP2_IMM | (imm >> 24) | ((rol & 0xf) << 8);
     184            imm2 = Op2Immediate | (imm >> 24) | ((rol & 0xf) << 8);
    185185        else
    186186            return 0;
    … …  
    204204    // Do it by 1 instruction
    205205    tmp = getOp2(imm);
    206     if (tmp != INVALID_IMM)
     206    if (tmp != InvalidImmediate)
    207207        return tmp;
    208208
    209209    tmp = getOp2(~imm);
    210     if (tmp != INVALID_IMM) {
     210    if (tmp != InvalidImmediate) {
    211211        if (invert)
    212             return tmp | OP2_INV_IMM;
     212            return tmp | Op2InvertedImmediate;
    213213        mvn_r(tmpReg, tmp);
    214214        return tmpReg;
    … …  
    224224    // Do it by 1 instruction
    225225    tmp = getOp2(imm);
    226     if (tmp != INVALID_IMM) {
     226    if (tmp != InvalidImmediate) {
    227227        mov_r(dest, tmp);
    228228        return;
    … …  
    230230
    231231    tmp = getOp2(~imm);
    232     if (tmp != INVALID_IMM) {
     232    if (tmp != InvalidImmediate) {
    233233        mvn_r(dest, tmp);
    234234        return;
    … …  
    242242#if WTF_ARM_ARCH_AT_LEAST(7)
    243243    ARMWord tmp = getImm16Op2(imm);
    244     if (tmp != INVALID_IMM) {
     244    if (tmp != InvalidImmediate) {
    245245        movw_r(dest, tmp);
    246246        return dest;
    … …  
    269269            dtr_u(transferType, srcDst, base, offset);
    270270        else if (offset <= 0xfffff) {
    271             add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
     271            add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));
    272272            dtr_u(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
    273273        } else {
    … …  
    279279            dtr_d(transferType, srcDst, base, -offset);
    280280        else if (offset >= -0xfffff) {
    281             sub_r(ARMRegisters::S0, base, OP2_IMM | (-offset >> 12) | (10 << 8));
     281            sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));
    282282            dtr_d(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
    283283        } else {
    … …  
    308308            dtrh_u(transferType, srcDst, base, getOp2Half(offset));
    309309        else if (offset <= 0xffff) {
    310             add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 8) | (12 << 8));
     310            add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));
    311311            dtrh_u(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
    312312        } else {
    … …  
    318318            dtrh_d(transferType, srcDst, base, getOp2Half(-offset));
    319319        else if (offset >= -0xffff) {
    320             sub_r(ARMRegisters::S0, base, OP2_IMM | (-offset >> 8) | (12 << 8));
     320            sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));
    321321            dtrh_d(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
    322322        } else {
    … …  
    347347        }
    348348        if (offset <= 0x3ffff && offset >= 0) {
    349             add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 10) | (11 << 8));
     349            add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
    350350            fdtr_u(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    351351            return;
    … …  
    358358        }
    359359        if (offset <= 0x3ffff && offset >= 0) {
    360             sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 10) | (11 << 8));
     360            sub_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
    361361            fdtr_d(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    362362            return;
    … …  
    393393        if (*addr != InvalidBranchTarget) {
    394394            if (!(iter->m_offset & 1)) {
    395                 intptr_t difference = reinterpret_cast_ptr<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetching);
    396 
    397                 if ((difference <= BOFFSET_MAX && difference >= BOFFSET_MIN)) {
    398                     *ldrAddr = B | getConditionalField(*ldrAddr) | (difference & BRANCH_MASK);
     395                intptr_t difference = reinterpret_cast_ptr<ARMWord*>(data + *addr) - (ldrAddr + DefaultPrefetchOffset);
     396
     397                if ((difference <= MaximumBranchOffsetDistance && difference >= MinimumBranchOffsetDistance)) {
     398                    *ldrAddr = B | getConditionalField(*ldrAddr) | (difference & BranchOffsetMask);
    399399                    continue;
    400400                }
Note: See TracChangeset for help on using the changeset viewer.