Ignore:
Timestamp:
Aug 14, 2012, 4:28:25 AM (13 years ago)
Author:
[email protected]
Message:

Rename functions in the ARM port of DFG-JIT for better code readability.
​https://bugs.webkit.org/show_bug.cgi?id=93609

Patch by Gabor Ballabas <​[email protected]> on 2012-08-14
Reviewed by Zoltan Herczeg.

Rename functions in the ARM port of DFG-JIT for better code
readability, and for following the WebKit coding style
wherever it is possible.

  • assembler/ARMAssembler.cpp:

(JSC::ARMAssembler::genInt):
(JSC::ARMAssembler::getImm):
(JSC::ARMAssembler::moveImm):
(JSC::ARMAssembler::encodeComplexImm):
(JSC::ARMAssembler::dataTransfer32):
(JSC::ARMAssembler::baseIndexTransfer32):
(JSC::ARMAssembler::dataTransfer16):
(JSC::ARMAssembler::baseIndexTransfer16):
(JSC::ARMAssembler::dataTransferFloat):
(JSC::ARMAssembler::baseIndexTransferFloat):

  • assembler/ARMAssembler.h:

(JSC::ARMAssembler::bitAnd):
(JSC::ARMAssembler::bitAnds):
(JSC::ARMAssembler::eor):
(JSC::ARMAssembler::eors):
(JSC::ARMAssembler::sub):
(JSC::ARMAssembler::subs):
(JSC::ARMAssembler::rsb):
(JSC::ARMAssembler::rsbs):
(JSC::ARMAssembler::add):
(JSC::ARMAssembler::adds):
(JSC::ARMAssembler::adc):
(JSC::ARMAssembler::adcs):
(JSC::ARMAssembler::sbc):
(JSC::ARMAssembler::sbcs):
(JSC::ARMAssembler::rsc):
(JSC::ARMAssembler::rscs):
(JSC::ARMAssembler::tst):
(JSC::ARMAssembler::teq):
(JSC::ARMAssembler::cmp):
(JSC::ARMAssembler::cmn):
(JSC::ARMAssembler::orr):
(JSC::ARMAssembler::orrs):
(JSC::ARMAssembler::mov):
(JSC::ARMAssembler::movw):
(JSC::ARMAssembler::movt):
(JSC::ARMAssembler::movs):
(JSC::ARMAssembler::bic):
(JSC::ARMAssembler::bics):
(JSC::ARMAssembler::mvn):
(JSC::ARMAssembler::mvns):
(JSC::ARMAssembler::mul):
(JSC::ARMAssembler::muls):
(JSC::ARMAssembler::mull):
(JSC::ARMAssembler::vmov_f64):
(JSC::ARMAssembler::vadd_f64):
(JSC::ARMAssembler::vdiv_f64):
(JSC::ARMAssembler::vsub_f64):
(JSC::ARMAssembler::vmul_f64):
(JSC::ARMAssembler::vcmp_f64):
(JSC::ARMAssembler::vsqrt_f64):
(JSC::ARMAssembler::vabs_f64):
(JSC::ARMAssembler::vneg_f64):
(JSC::ARMAssembler::ldrImmediate):
(JSC::ARMAssembler::ldrUniqueImmediate):
(JSC::ARMAssembler::dtrUp):
(JSC::ARMAssembler::dtrUpRegister):
(JSC::ARMAssembler::dtrDown):
(JSC::ARMAssembler::dtrDownRegister):
(JSC::ARMAssembler::halfDtrUp):
(JSC::ARMAssembler::halfDtrUpRegister):
(JSC::ARMAssembler::halfDtrDown):
(JSC::ARMAssembler::halfDtrDownRegister):
(JSC::ARMAssembler::doubleDtrUp):
(JSC::ARMAssembler::doubleDtrDown):
(JSC::ARMAssembler::push):
(JSC::ARMAssembler::pop):
(JSC::ARMAssembler::poke):
(JSC::ARMAssembler::peek):
(JSC::ARMAssembler::vmov_vfp64):
(JSC::ARMAssembler::vmov_arm64):
(JSC::ARMAssembler::vmov_vfp32):
(JSC::ARMAssembler::vmov_arm32):
(JSC::ARMAssembler::vcvt_f64_s32):
(JSC::ARMAssembler::vcvt_s32_f64):
(JSC::ARMAssembler::vcvt_u32_f64):
(JSC::ARMAssembler::vcvt_f64_f32):
(JSC::ARMAssembler::vcvt_f32_f64):
(JSC::ARMAssembler::clz):
(JSC::ARMAssembler::lslRegister):
(JSC::ARMAssembler::lsrRegister):
(JSC::ARMAssembler::asrRegister):
(JSC::ARMAssembler::align):
(JSC::ARMAssembler::loadBranchTarget):
(JSC::ARMAssembler::vmov):

  • assembler/MacroAssemblerARM.cpp:

(JSC::MacroAssemblerARM::load32WithUnalignedHalfWords):

  • assembler/MacroAssemblerARM.h:

(JSC::MacroAssemblerARM::add32):
(JSC::MacroAssemblerARM::and32):
(JSC::MacroAssemblerARM::lshift32):
(JSC::MacroAssemblerARM::mul32):
(JSC::MacroAssemblerARM::or32):
(JSC::MacroAssemblerARM::rshift32):
(JSC::MacroAssemblerARM::urshift32):
(JSC::MacroAssemblerARM::sub32):
(JSC::MacroAssemblerARM::xor32):
(JSC::MacroAssemblerARM::countLeadingZeros32):
(JSC::MacroAssemblerARM::convertibleLoadPtr):
(JSC::MacroAssemblerARM::load32WithAddressOffsetPatch):
(JSC::MacroAssemblerARM::load32WithCompactAddressOffsetPatch):
(JSC::MacroAssemblerARM::store32WithAddressOffsetPatch):
(JSC::MacroAssemblerARM::store32):
(JSC::MacroAssemblerARM::pop):
(JSC::MacroAssemblerARM::push):
(JSC::MacroAssemblerARM::move):
(JSC::MacroAssemblerARM::swap):
(JSC::MacroAssemblerARM::branch32):
(JSC::MacroAssemblerARM::branchTest32):
(JSC::MacroAssemblerARM::mull32):
(JSC::MacroAssemblerARM::branchSub32):
(JSC::MacroAssemblerARM::compare32):
(JSC::MacroAssemblerARM::test32):
(JSC::MacroAssemblerARM::load32):
(JSC::MacroAssemblerARM::relativeTableJump):
(JSC::MacroAssemblerARM::moveWithPatch):
(JSC::MacroAssemblerARM::loadDouble):
(JSC::MacroAssemblerARM::moveDouble):
(JSC::MacroAssemblerARM::addDouble):
(JSC::MacroAssemblerARM::divDouble):
(JSC::MacroAssemblerARM::subDouble):
(JSC::MacroAssemblerARM::mulDouble):
(JSC::MacroAssemblerARM::sqrtDouble):
(JSC::MacroAssemblerARM::absDouble):
(JSC::MacroAssemblerARM::negateDouble):
(JSC::MacroAssemblerARM::convertInt32ToDouble):
(JSC::MacroAssemblerARM::convertFloatToDouble):
(JSC::MacroAssemblerARM::convertDoubleToFloat):
(JSC::MacroAssemblerARM::branchDouble):
(JSC::MacroAssemblerARM::branchTruncateDoubleToInt32):
(JSC::MacroAssemblerARM::branchTruncateDoubleToUint32):
(JSC::MacroAssemblerARM::truncateDoubleToInt32):
(JSC::MacroAssemblerARM::truncateDoubleToUint32):
(JSC::MacroAssemblerARM::branchConvertDoubleToInt32):
(JSC::MacroAssemblerARM::branchDoubleNonZero):
(JSC::MacroAssemblerARM::branchDoubleZeroOrNaN):

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/Source/JavaScriptCore/assembler/ARMAssembler.cpp

    r124930 r125541  
    188188
    189189    if (positive) {
    190         mov_r(reg, imm1);
    191         orr_r(reg, reg, imm2);
     190        mov(reg, imm1);
     191        orr(reg, reg, imm2);
    192192    } else {
    193         mvn_r(reg, imm1);
    194         bic_r(reg, reg, imm2);
     193        mvn(reg, imm1);
     194        bic(reg, reg, imm2);
    195195    }
    196196
    … …  
    211211        if (invert)
    212212            return tmp | Op2InvertedImmediate;
    213         mvn_r(tmpReg, tmp);
     213        mvn(tmpReg, tmp);
    214214        return tmpReg;
    215215    }
    … …  
    225225    tmp = getOp2(imm);
    226226    if (tmp != InvalidImmediate) {
    227         mov_r(dest, tmp);
     227        mov(dest, tmp);
    228228        return;
    229229    }
    … …  
    231231    tmp = getOp2(~imm);
    232232    if (tmp != InvalidImmediate) {
    233         mvn_r(dest, tmp);
     233        mvn(dest, tmp);
    234234        return;
    235235    }
    … …  
    243243    ARMWord tmp = getImm16Op2(imm);
    244244    if (tmp != InvalidImmediate) {
    245         movw_r(dest, tmp);
     245        movw(dest, tmp);
    246246        return dest;
    247247    }
    248     movw_r(dest, getImm16Op2(imm & 0xffff));
    249     movt_r(dest, getImm16Op2(imm >> 16));
     248    movw(dest, getImm16Op2(imm & 0xffff));
     249    movt(dest, getImm16Op2(imm >> 16));
    250250    return dest;
    251251#else
    … …  
    256256        return dest;
    257257
    258     ldr_imm(dest, imm);
     258    ldrImmediate(dest, imm);
    259259    return dest;
    260260#endif
    … …  
    267267    if (offset >= 0) {
    268268        if (offset <= 0xfff)
    269             dtr_u(transferType, srcDst, base, offset);
     269            dtrUp(transferType, srcDst, base, offset);
    270270        else if (offset <= 0xfffff) {
    271             add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));
    272             dtr_u(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
     271            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 12) | (10 << 8));
     272            dtrUp(transferType, srcDst, ARMRegisters::S0, (offset & 0xfff));
    273273        } else {
    274274            moveImm(offset, ARMRegisters::S0);
    275             dtr_ur(transferType, srcDst, base, ARMRegisters::S0);
     275            dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    276276        }
    277277    } else {
    278278        if (offset >= -0xfff)
    279             dtr_d(transferType, srcDst, base, -offset);
     279            dtrDown(transferType, srcDst, base, -offset);
    280280        else if (offset >= -0xfffff) {
    281             sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));
    282             dtr_d(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
     281            sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 12) | (10 << 8));
     282            dtrDown(transferType, srcDst, ARMRegisters::S0, (-offset & 0xfff));
    283283        } else {
    284284            moveImm(offset, ARMRegisters::S0);
    285             dtr_ur(transferType, srcDst, base, ARMRegisters::S0);
     285            dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    286286        }
    287287    }
    … …  
    294294
    295295    if (!offset) {
    296         dtr_ur(transferType, srcDst, base, op2);
     296        dtrUpRegister(transferType, srcDst, base, op2);
    297297        return;
    298298    }
    299299
    300     add_r(ARMRegisters::S1, base, op2);
     300    add(ARMRegisters::S1, base, op2);
    301301    dataTransfer32(transferType, srcDst, ARMRegisters::S1, offset);
    302302}
    … …  
    306306    if (offset >= 0) {
    307307        if (offset <= 0xff)
    308             dtrh_u(transferType, srcDst, base, getOp2Half(offset));
     308            halfDtrUp(transferType, srcDst, base, getOp2Half(offset));
    309309        else if (offset <= 0xffff) {
    310             add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));
    311             dtrh_u(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
     310            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 8) | (12 << 8));
     311            halfDtrUp(transferType, srcDst, ARMRegisters::S0, getOp2Half(offset & 0xff));
    312312        } else {
    313313            moveImm(offset, ARMRegisters::S0);
    314             dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);
     314            halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    315315        }
    316316    } else {
    317317        if (offset >= -0xff)
    318             dtrh_d(transferType, srcDst, base, getOp2Half(-offset));
     318            halfDtrDown(transferType, srcDst, base, getOp2Half(-offset));
    319319        else if (offset >= -0xffff) {
    320             sub_r(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));
    321             dtrh_d(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
     320            sub(ARMRegisters::S0, base, Op2Immediate | (-offset >> 8) | (12 << 8));
     321            halfDtrDown(transferType, srcDst, ARMRegisters::S0, getOp2Half(-offset & 0xff));
    322322        } else {
    323323            moveImm(offset, ARMRegisters::S0);
    324             dtrh_ur(transferType, srcDst, base, ARMRegisters::S0);
     324            halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0);
    325325        }
    326326    }
    … …  
    330330{
    331331    if (!scale && !offset) {
    332         dtrh_ur(transferType, srcDst, base, index);
     332        halfDtrUpRegister(transferType, srcDst, base, index);
    333333        return;
    334334    }
    335335
    336     add_r(ARMRegisters::S1, base, lsl(index, scale));
     336    add(ARMRegisters::S1, base, lsl(index, scale));
    337337    dataTransfer16(transferType, srcDst, ARMRegisters::S1, offset);
    338338}
    … …  
    343343    if (!(offset & 0x3)) {
    344344        if (offset <= 0x3ff && offset >= 0) {
    345             fdtr_u(transferType, srcDst, base, offset >> 2);
     345            doubleDtrUp(transferType, srcDst, base, offset >> 2);
    346346            return;
    347347        }
    348348        if (offset <= 0x3ffff && offset >= 0) {
    349             add_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
    350             fdtr_u(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
     349            add(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
     350            doubleDtrUp(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    351351            return;
    352352        }
    … …  
    354354
    355355        if (offset <= 0x3ff && offset >= 0) {
    356             fdtr_d(transferType, srcDst, base, offset >> 2);
     356            doubleDtrDown(transferType, srcDst, base, offset >> 2);
    357357            return;
    358358        }
    359359        if (offset <= 0x3ffff && offset >= 0) {
    360             sub_r(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
    361             fdtr_d(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
     360            sub(ARMRegisters::S0, base, Op2Immediate | (offset >> 10) | (11 << 8));
     361            doubleDtrDown(transferType, srcDst, ARMRegisters::S0, (offset >> 2) & 0xff);
    362362            return;
    363363        }
    … …  
    366366
    367367    moveImm(offset, ARMRegisters::S0);
    368     add_r(ARMRegisters::S0, ARMRegisters::S0, base);
    369     fdtr_u(transferType, srcDst, ARMRegisters::S0, 0);
     368    add(ARMRegisters::S0, ARMRegisters::S0, base);
     369    doubleDtrUp(transferType, srcDst, ARMRegisters::S0, 0);
    370370}
    371371
    372372void ARMAssembler::baseIndexTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, RegisterID index, int scale, int32_t offset)
    373373{
    374     add_r(ARMRegisters::S1, base, lsl(index, scale));
     374    add(ARMRegisters::S1, base, lsl(index, scale));
    375375    dataTransferFloat(transferType, srcDst, ARMRegisters::S1, offset);
    376376}
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