Verilog coding of demux 8 x1
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Verilog coding of demux 8 x1
![Verilog coding of DEMUX 1X8 using if else statement
module demux(d, sel, z);
input d;
input [2:0] sel;
output [7:0] z;
reg [7:0] z;
always @( d or sel)
begin
if( sel==3'b000)
z[0]=d;
else if( sel==3'b001)
z[1]=d;
else if( sel==3'b010)
z[2]=d;
else if( sel==3'b011)
z[3]=d;
else if( sel==3'b100)
z[4]=d;
else if( sel==3'b101)
z[5]=d;
else if( sel==3'b110)
z[6]=d;
else
z[7]=d;
end
endmodule](https://image.slidesharecdn.com/verilog-coding-of-de-mux-8x1-160216065025/85/Verilog-coding-of-demux-8-x1-1-320.jpg)
![Verilog coding of DEMUX 1X8 using case statement
module demux(d, sel, z);
input d;
input [2:0] sel;
output [7:0] z;
reg [7:0] z;
always @( d or sel)
begin
case(sel)
3'b000 : z[0] = d;
3'b001 : z[1] = d;
3'b010 : z[2] = d;
3'b011 : z[3] = d;
3'b100 : z[4] = d;
3'b101 : z[5] = d;
3'b110 : z[6] = d;
3'b111 : z[7] = d;
endcase
end
endmodule](https://image.slidesharecdn.com/verilog-coding-of-de-mux-8x1-160216065025/85/Verilog-coding-of-demux-8-x1-2-320.jpg)
Verilog coding of demux 8 x1
- 1. Verilog coding of DEMUX 1X8 using if else statement module demux(d, sel, z); input d; input [2:0] sel; output [7:0] z; reg [7:0] z; always @( d or sel) begin if( sel==3'b000) z[0]=d; else if( sel==3'b001) z[1]=d; else if( sel==3'b010) z[2]=d; else if( sel==3'b011) z[3]=d; else if( sel==3'b100) z[4]=d; else if( sel==3'b101) z[5]=d; else if( sel==3'b110) z[6]=d; else z[7]=d; end endmodule
- 2. Verilog coding of DEMUX 1X8 using case statement module demux(d, sel, z); input d; input [2:0] sel; output [7:0] z; reg [7:0] z; always @( d or sel) begin case(sel) 3'b000 : z[0] = d; 3'b001 : z[1] = d; 3'b010 : z[2] = d; 3'b011 : z[3] = d; 3'b100 : z[4] = d; 3'b101 : z[5] = d; 3'b110 : z[6] = d; 3'b111 : z[7] = d; endcase end endmodule