Changeset 149676 in webkit for trunk/Source/JavaScriptCore/assembler/SH4Assembler.h

Timestamp:

May 7, 2013, 9:53:23 AM (12 years ago)

Author:

[email protected]

Message:

Take advantage of pre-decrement and post-increment opcodes for sh4 base JIT.
​https://bugs.webkit.org/show_bug.cgi?id=115722

Patch by Julien Brianceau <​[email protected]> on 2013-05-07
Reviewed by Oliver Hunt.

• assembler/MacroAssemblerSH4.h:

(JSC::MacroAssemblerSH4::load8PostInc):
(MacroAssemblerSH4):
(JSC::MacroAssemblerSH4::load16Unaligned):
(JSC::MacroAssemblerSH4::load16PostInc):
(JSC::MacroAssemblerSH4::storeDouble):
(JSC::MacroAssemblerSH4::load32WithUnalignedHalfWords):

• assembler/SH4Assembler.h:

(JSC::SH4Assembler::movwMemRegIn):
(SH4Assembler):
(JSC::SH4Assembler::movbMemRegIn):
(JSC::SH4Assembler::printInstr):

File:

• trunk/Source/JavaScriptCore/assembler/SH4Assembler.h (modified) (4 diffs)

trunk/Source/JavaScriptCore/assembler/SH4Assembler.h

@@ -118 +118 @@
     MOVW_WRITE_R0RN_OPCODE = 0x0005,
     MOVW_READ_RM_OPCODE = 0x6001,
+    MOVW_READ_RMINC_OPCODE = 0x6005,
     MOVW_READ_R0RM_OPCODE = 0x000d,
     MOVW_READ_OFFRM_OPCODE = 0x8500,
@@ -1039 +1040 @@
     }
 
+    void movwMemRegIn(RegisterID base, RegisterID dst)
+    {
+        uint16_t opc = getOpcodeGroup1(MOVW_READ_RMINC_OPCODE, dst, base);
+        oneShortOp(opc);
+    }
+
     void movwPCReg(int offset, RegisterID base, RegisterID dst)
     {
@@ -1131 +1138 @@
     {
         uint16_t opc = getOpcodeGroup1(MOVB_READ_RM_OPCODE, dst, src);
+        oneShortOp(opc);
+    }
+
+    void movbMemRegIn(RegisterID base, RegisterID dst)
+    {
+        uint16_t opc = getOpcodeGroup1(MOVB_READ_RMINC_OPCODE, dst, base);
         oneShortOp(opc);
     }
@@ -1959 +1972 @@
             format = "    MOV.W @R%d, R%d\n";
             break;
+        case MOVW_READ_RMINC_OPCODE:
+            format = "    MOV.W @R%d+, R%d\n";
+            break;
         case MOVW_READ_R0RM_OPCODE:
             format = "    MOV.W @(R0, R%d), R%d\n";